linux-kernel - Re: [PATCH V2] arm64: dts: ti: k3-j7200: Correct the d-cache-sets info

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Message-ID: <20211203114611.dqorti3g6q7k64sz@ti.com>
Date:   Fri, 3 Dec 2021 17:16:13 +0530
From:   Pratyush Yadav <p.yadav@...com>
To:     Nishanth Menon <nm@...com>
CC:     Rob Herring <robh+dt@...nel.org>, Tero Kristo <kristo@...nel.org>,
        Vignesh Raghavendra <vigneshr@...com>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-omap@...r.kernel.org>, Peng Fan <peng.fan@....com>
Subject: Re: [PATCH V2] arm64: dts: ti: k3-j7200: Correct the d-cache-sets
 info

On 12/11/21 10:26PM, Nishanth Menon wrote:
> A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
>  - ICache is 3-way set-associative
>  - Dcache is 2-way set-associative
>  - Line size are 64bytes
> 
> 32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways
> 512 ways / 2 (Dcache is 2-way per set) = 256 sets.
> 
> So, correct the d-cache-sets info.
> 
> [1] https://www.ti.com/lit/pdf/spruiu1
> 
> Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
> Reported-by: Peng Fan <peng.fan@....com>
> Signed-off-by: Nishanth Menon <nm@...com>

Reviewed-by: Pratyush Yadav <p.yadav@...com>

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.