linux-kernel - Re: [PATCH v6 5/5] clk: qcom: Add support for SDX65 RPMh clocks

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Date:   Fri, 3 Dec 2021 10:23:57 -0600
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     quic_vamslank@...cinc.com
Cc:     agross@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
        robh+dt@...nel.org, tglx@...utronix.de, maz@...nel.org,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        manivannan.sadhasivam@...aro.org, Vinod Koul <vkoul@...nel.org>
Subject: Re: [PATCH v6 5/5] clk: qcom: Add support for SDX65 RPMh clocks

On Wed 01 Dec 18:21 CST 2021, quic_vamslank@...cinc.com wrote:

> From: Vamsi krishna Lanka <quic_vamslank@...cinc.com>
> 
> Add support for clocks maintained by RPMh in SDX65 SoCs.
> 
> Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@...cinc.com>
> Acked-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> Reviewed-by: Vinod Koul <vkoul@...nel.org>

The two RPMh patches are independent of the PLL/GCC patches, so I have
picked up the RPMh patches from this series.

Please respin the PLL & GCC patches per Stephen's feedback.


PS. checkpatch --strict complains that the author signature doesn't
match the Signed-off-by, because you have a lowercase 'k' in the From,
but uppercase in the s-o-b. Can you please make sure the two matches in
the future?

Thanks,
Bjorn

> ---
>  drivers/clk/qcom/clk-rpmh.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 441d7a20e6f3..30b26fb96514 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -556,6 +556,30 @@ static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
>  	.num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
>  };
>  
> +DEFINE_CLK_RPMH_VRM(sdx65, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 4);
> +
> +static struct clk_hw *sdx65_rpmh_clocks[] = {
> +	[RPMH_CXO_CLK]          = &sc7280_bi_tcxo.hw,
> +	[RPMH_CXO_CLK_A]        = &sc7280_bi_tcxo_ao.hw,
> +	[RPMH_LN_BB_CLK1]       = &sdx65_ln_bb_clk1.hw,
> +	[RPMH_LN_BB_CLK1_A]     = &sdx65_ln_bb_clk1_ao.hw,
> +	[RPMH_RF_CLK1]          = &sdm845_rf_clk1.hw,
> +	[RPMH_RF_CLK1_A]        = &sdm845_rf_clk1_ao.hw,
> +	[RPMH_RF_CLK2]          = &sdm845_rf_clk2.hw,
> +	[RPMH_RF_CLK2_A]        = &sdm845_rf_clk2_ao.hw,
> +	[RPMH_RF_CLK3]          = &sdm845_rf_clk3.hw,
> +	[RPMH_RF_CLK3_A]        = &sdm845_rf_clk3_ao.hw,
> +	[RPMH_RF_CLK4]          = &sm8350_rf_clk4.hw,
> +	[RPMH_RF_CLK4_A]        = &sm8350_rf_clk4_ao.hw,
> +	[RPMH_IPA_CLK]          = &sdm845_ipa.hw,
> +	[RPMH_QPIC_CLK]         = &sdx55_qpic_clk.hw,
> +};
> +
> +static const struct clk_rpmh_desc clk_rpmh_sdx65 = {
> +	.clks = sdx65_rpmh_clocks,
> +	.num_clks = ARRAY_SIZE(sdx65_rpmh_clocks),
> +};
> +
>  static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
>  					 void *data)
>  {
> @@ -643,6 +667,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
>  	{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
>  	{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
>  	{ .compatible = "qcom,sdx55-rpmh-clk",  .data = &clk_rpmh_sdx55},
> +	{ .compatible = "qcom,sdx65-rpmh-clk",  .data = &clk_rpmh_sdx65},
>  	{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
>  	{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
>  	{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
> -- 
> 2.33.1
>