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Message-ID: <2519e6b6-4f74-e2f8-c428-0fceb0e16472@intel.com>
Date: Fri, 3 Dec 2021 16:20:34 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Thomas Gleixner <tglx@...utronix.de>
Cc: Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"Rafael J . Wysocki" <rjw@...ysocki.net>,
"H . Peter Anvin" <hpa@...or.com>, Tony Luck <tony.luck@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Andi Kleen <ak@...ux.intel.com>,
Kuppuswamy Sathyanarayanan <knsathya@...nel.org>,
linux-kernel@...r.kernel.org, linux-acpi@...r.kernel.org
Subject: Re: [PATCH v2] x86: Skip WBINVD instruction for VM guest
On 12/3/21 3:49 PM, Kirill A. Shutemov wrote:
> - ACPI_FLUSH_CPU_CACHE();
> + if (acpi_state >= ACPI_STATE_S1 && acpi_state <= ACPI_STATE_S3)
> + ACPI_FLUSH_CPU_CACHE();
It's a bit of a bummer that this per-sleep-state logic has to be
repeated so many time.
If you pass acpi_state into ACPI_FLUSH_CPU_CACHE() can you centralize
the set of places where that knowledge about which sleep states require
flushing?
> TDX doesn't support these S- and C-states. TDX is only supports S0 and S5.
This makes me a bit nervous. Is this "the first TDX implementation
supports..." or "the TDX architecture *prohibits* supporting S1 (or
whatever"?
I really think we need some kind of architecture guarantee. Without
that, we risk breaking things if someone at our employer simply changes
their mind.
The:
> #define ACPI_FLUSH_CPU_CACHE_PHYS() \
> if (!cpu_feature_enabled(XXX)) \
> wbinvd(); \
does seem simpler and less error-prone than this, though.
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