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Message-ID: <CACRpkdbVfpmFKcdmNtcbpozuMt+EeJSmCuF4nJ--8oHrnyvLEA@mail.gmail.com>
Date: Sun, 5 Dec 2021 00:37:52 +0100
From: Linus Walleij <linus.walleij@...aro.org>
To: Herve Codina <herve.codina@...tlin.com>
Cc: Viresh Kumar <vireshk@...nel.org>,
Shiraz Hashim <shiraz.linux.kernel@...il.com>, soc@...nel.org,
Rob Herring <robh+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH 5/6] irq: spear-shirq: Add support for IRQ 0..6
On Thu, Dec 2, 2021 at 10:53 AM Herve Codina <herve.codina@...tlin.com> wrote:
> IRQ 0..7 are not supported by the driver for SPEAr320 SOC family.
>
> IRQ 0 is not reserved in SPEAr320 SOC (assigned to GPIOINT).
> Furthermore, in SPEAr320s SOC variant, IRQ 0..6 are assigned
> as follow:
> IRQ 6 - NGPIO_INTR: Combined status of edge programmable
> interrupts from GPIO ports
> IRQ 5 - TX_OR_INTR: I2S interrupt on Transmit FIFO overrun
> IRQ 4 - TX_EMP_INTR: I2S interrupt on Transmit FIFO empty
> IRQ 3 - RX_OR_INTR: I2S interrupt on Receive FIFO overrun
> IRQ 2 - RX_DA_INTR: I2S interrupt on data available in Receive FIFO
> IRQ 1 - Reserved
> IRQ 0 - GPIO_INTR: Legacy interrupt from GPIO ports
>
> Add support for these IRQs in SPEAr320 SOC family.
>
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
Acked-by: Linus Walleij <linus.walleij@...aro.org>
Yours,
Linus Walleij
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