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Date: Mon, 6 Dec 2021 04:10:00 +0000
From: Joakim Zhang <qiangqing.zhang@....com>
To: Shawn Guo <shawnguo@...nel.org>
CC: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
dl-linux-imx <linux-imx@....com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO voltage
Hi Shawn,
> -----Original Message-----
> From: Shawn Guo <shawnguo@...nel.org>
> Sent: 2021年12月6日 10:06
> To: Joakim Zhang <qiangqing.zhang@....com>
> Cc: robh+dt@...nel.org; s.hauer@...gutronix.de; kernel@...gutronix.de;
> festevam@...il.com; dl-linux-imx <linux-imx@....com>;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org
> Subject: Re: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO
> voltage
>
> On Mon, Dec 06, 2021 at 01:59:18AM +0000, Joakim Zhang wrote:
> >
> > Hi Shawn,
> >
> > > -----Original Message-----
> > > From: Shawn Guo <shawnguo@...nel.org>
> > > Sent: 2021年12月6日 9:16
> > > To: Joakim Zhang <qiangqing.zhang@....com>
> > > Cc: robh+dt@...nel.org; s.hauer@...gutronix.de;
> > > kernel@...gutronix.de; festevam@...il.com; dl-linux-imx
> > > <linux-imx@....com>; devicetree@...r.kernel.org;
> > > linux-kernel@...r.kernel.org
> > > Subject: Re: [PATCH 4/7] arm64: dts: imx8m: configure FEC PHY VDDIO
> > > voltage
> > >
> > > On Tue, Nov 23, 2021 at 04:05:03PM +0800, Joakim Zhang wrote:
> > > > As commit 2f664823a470 ("net: phy: at803x: add device tree
> > > > binding") described, configure FEC PHY VDDIO voltage according to
> board design.
> > > >
> > > > Signed-off-by: Joakim Zhang <qiangqing.zhang@....com>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 6 ++++++
> > > > arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 6 ++++++
> > > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 4 ++++
> > > > 3 files changed, 16 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > index 50b3bbb662d5..3bac87b7e142 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> > > > @@ -117,6 +117,12 @@
> > > > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > > > reset-assert-us = <10000>;
> > > > qca,disable-smarteee;
> > > > + vddio-supply = <&vddio>;
> > > > +
> > > > + vddio: vddio-regulator {
> > > > + regulator-min-microvolt = <1800000>;
> > > > + regulator-max-microvolt = <1800000>;
> > > > + };
> > > > };
> > > > };
> > > > };
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > index 342f57e8cf61..c3f15192b76c 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> > > > @@ -100,6 +100,12 @@
> > > > reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
> > > > reset-assert-us = <10000>;
> > > > qca,disable-smarteee;
> > > > + vddio-supply = <&vddio>;
> > > > +
> > > > + vddio: vddio-regulator {
> > > > + regulator-min-microvolt = <1800000>;
> > > > + regulator-max-microvolt = <1800000>;
> > > > + };
> > > > };
> > > > };
> > > > };
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > index a9e33548a2f3..c96d23fe3010 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> > > > @@ -170,6 +170,10 @@
> > > > reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
> > > > reset-assert-us = <10000>;
> > > > qca,disable-smarteee;
> > > > + vddio-supply = <&vddh>;
> > > > +
> > > > + vddh: vddh-regulator {
> > > > + };
> > >
> > > Why does this need to be different from the one on imx8mm-evk and
> > > imx8mn-evk?
> >
> > It's depend on RGMII_IO voltage out from SoC and PHY reference design.
> >
> > For 8MM/MN:
> > SoC RGMII_IO is 1.8V, and board design use "Reference Design, 1.5/1.8
> V RGMII I/O", PHY default work on 1.5V, so we need configure PHY to work
> on 1.8V.
> > For 8MQ:
> > SoC RGMII_IO is 2.5V, and board design use "Reference Design, 2.5 V/
> 3.3 V RGMII I/O", PHY default work on 2.5V.
>
> Hmm, why do you not specify 2.5V with regulator-min[max]-microvolt then?
> Also, why is the regulator named vddh instead of vddio?
The RGMII I/O voltage at PHY side could from VDDIO_REG or VDDH_REG, it depends on
how the design of board according to AT8031 block guide.
And the phy driver implement this align to the phy guide.
Could you please have a look at the commit or the binding?
commit 2f664823a47021ae029fe91272adbf0a223e477f
Author: Michael Walle <michael@...le.cc>
Date: Wed Nov 6 23:36:14 2019 +0100
net: phy: at803x: add device tree binding
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
Signed-off-by: Michael Walle <michael@...le.cc>
Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
Signed-off-by: David S. Miller <davem@...emloft.net>
Documentation/devicetree/bindings/net/qca,ar803x.yaml
vddio-regulator and vddh-regulator
Best Regards,
Joakim Zhang
> Shawn
>
> >
> > Best Regards,
> > Joakim Zhang
> > > Shawn
> > >
> > > > };
> > > > };
> > > > };
> > > > --
> > > > 2.17.1
> > > >
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