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Message-Id: <20211206182616.2089677-14-f.fainelli@gmail.com>
Date: Mon, 6 Dec 2021 10:26:15 -0800
From: Florian Fainelli <f.fainelli@...il.com>
To: devicetree@...r.kernel.org
Cc: Florian Fainelli <f.fainelli@...il.com>,
Damien Le Moal <damien.lemoal@...nsource.wdc.com>,
Rob Herring <robh+dt@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
bcm-kernel-feedback-list@...adcom.com (maintainer:BROADCOM BCM7XXX ARM
ARCHITECTURE), Gregory Fong <gregory.0xf0@...il.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Ulf Hansson <ulf.hansson@...aro.org>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Lee Jones <lee.jones@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Herbert Xu <herbert@...dor.apana.org.au>,
Ray Jui <rjui@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
Alessandro Zummo <a.zummo@...ertech.it>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Amit Kucheria <amitk@...nel.org>,
Zhang Rui <rui.zhang@...el.com>,
Markus Mayer <mmayer@...adcom.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Al Cooper <alcooperx@...il.com>,
Doug Berger <opendmb@...il.com>,
linux-ide@...r.kernel.org (open list:LIBATA SUBSYSTEM (Serial and
Parallel ATA drivers)), linux-kernel@...r.kernel.org (open list),
linux-gpio@...r.kernel.org (open list:GPIO SUBSYSTEM),
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ARM ARCHITECTURE),
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Subject: [PATCH v2 13/14] dt-bindings: bus: Convert GISB arbiter to YAML
Convert the Broadcom STB GISB bus arbiter to YAML to help with
validation.
Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
.../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ----------
.../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++
2 files changed, 66 insertions(+), 34 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
deleted file mode 100644
index 10f6d0a8159d..000000000000
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Broadcom GISB bus Arbiter controller
-
-Required properties:
-
-- compatible:
- "brcm,bcm7278-gisb-arb" for V7 28nm chips
- "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
- "brcm,bcm7435-gisb-arb" for newer 40nm chips
- "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
- "brcm,bcm7038-gisb-arb" for 130nm chips
-- reg: specifies the base physical address and size of the registers
-- interrupts: specifies the two interrupts (timeout and TEA) to be used from
- the parent interrupt controller. A third optional interrupt may be specified
- for breakpoints.
-
-Optional properties:
-
-- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
- masters are valid at the system level
-- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
- masters. Should match the number of bits set in brcm,gisb-master-mask and
- the order in which they appear
-
-Example:
-
-gisb-arb@...00000 {
- compatible = "brcm,gisb-arb";
- reg = <0xf0400000 0x800>;
- interrupts = <0>, <2>;
- interrupt-parent = <&sun_l2_intc>;
-
- brcm,gisb-arb-master-mask = <0x7>;
- brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
-};
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
new file mode 100644
index 000000000000..483b019275cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom GISB bus Arbiter controller
+
+maintainers:
+ - Florian Fainelli <f.fainelli@...il.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7445-gisb-arb
+ - const: brcm,gisb-arb
+ - items:
+ - const: brcm,bcm7278-gisb-arb
+ - items:
+ - const: brcm,bcm7435-gisb-arb
+ - items:
+ - const: brcm,bcm7400-gisb-arb
+ - items:
+ - const: brcm,bcm7038-gisb-arb
+ - items:
+ - const: brcm,gisb-arb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 3
+
+ brcm,gisb-arb-master-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ 32-bits wide bitmask used to specify which GISB masters are valid at the
+ system level
+
+ brcm,gisb-arb-master-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: >
+ String list of the litteral name of the GISB masters. Should match the
+ number of bits set in brcm,gisb-master-mask and the order in which they
+ appear
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ gisb-arb@...00000 {
+ compatible = "brcm,gisb-arb";
+ reg = <0xf0400000 0x800>;
+ interrupts = <0>, <2>;
+ interrupt-parent = <&sun_l2_intc>;
+ brcm,gisb-arb-master-mask = <0x7>;
+ brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
+ };
--
2.25.1
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