| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20211206182616.2089677-9-f.fainelli@gmail.com>
Date: Mon, 6 Dec 2021 10:26:10 -0800
From: Florian Fainelli <f.fainelli@...il.com>
To: devicetree@...r.kernel.org
Cc: Florian Fainelli <f.fainelli@...il.com>,
Damien Le Moal <damien.lemoal@...nsource.wdc.com>,
Rob Herring <robh+dt@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
bcm-kernel-feedback-list@...adcom.com (maintainer:BROADCOM BCM7XXX ARM
ARCHITECTURE), Gregory Fong <gregory.0xf0@...il.com>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Ulf Hansson <ulf.hansson@...aro.org>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Lee Jones <lee.jones@...aro.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Herbert Xu <herbert@...dor.apana.org.au>,
Ray Jui <rjui@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
Alessandro Zummo <a.zummo@...ertech.it>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Amit Kucheria <amitk@...nel.org>,
Zhang Rui <rui.zhang@...el.com>,
Markus Mayer <mmayer@...adcom.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Al Cooper <alcooperx@...il.com>,
Doug Berger <opendmb@...il.com>,
linux-ide@...r.kernel.org (open list:LIBATA SUBSYSTEM (Serial and
Parallel ATA drivers)), linux-kernel@...r.kernel.org (open list),
linux-gpio@...r.kernel.org (open list:GPIO SUBSYSTEM),
linux-arm-kernel@...ts.infradead.org (moderated list:BROADCOM BCM7XXX
ARM ARCHITECTURE),
linux-mmc@...r.kernel.org (open list:MULTIMEDIA CARD (MMC), SECURE
DIGITAL (SD) AND...),
linux-pwm@...r.kernel.org (open list:PWM SUBSYSTEM),
linux-crypto@...r.kernel.org (open list:HARDWARE RANDOM NUMBER
GENERATOR CORE),
linux-rtc@...r.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM),
linux-pm@...r.kernel.org (open list:THERMAL),
linux-usb@...r.kernel.org (open list:USB SUBSYSTEM)
Subject: [PATCH v2 08/14] dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120
The two bindings are very similar and should be covered by the same
document, do that so we can get rid of an additional binding file.
Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
.../brcm,bcm3380-l2-intc.txt | 39 -------------------
.../brcm,bcm7120-l2-intc.yaml | 30 +++++++++++++-
2 files changed, 28 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
deleted file mode 100644
index 37aea40d5430..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
-
-This interrupt controller shows up in various forms on many BCM338x/BCM63xx
-chipsets. It has the following properties:
-
-- outputs a single interrupt signal to its interrupt controller parent
-
-- contains one or more enable/status word pairs, which often appear at
- different offsets in different blocks
-
-- no atomic set/clear operations
-
-Required properties:
-
-- compatible: should be "brcm,bcm3380-l2-intc"
-- reg: specifies one or more enable/status pairs, in the following format:
- <enable_reg 0x4 status_reg 0x4>...
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line in the interrupt-parent controller
- node, valid values depend on the type of parent interrupt controller
-
-Optional properties:
-
-- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-Example:
-
-irq0_intc: interrupt-controller@...00020 {
- compatible = "brcm,bcm3380-l2-intc";
- reg = <0x10000024 0x4 0x1000002c 0x4>,
- <0x10000020 0x4 0x10000028 0x4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&cpu_intc>;
- interrupts = <2>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
index e0c6dce40d13..8be7fe29e6a9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Broadcom BCM7120-style Level 2 interrupt controller
+title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
maintainers:
- Florian Fainelli <f.fainelli@...il.com>
@@ -59,16 +59,31 @@ description: >
..
31 ........................ X
+ The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
+ on many BCM338x/BCM63xx chipsets. It has the following properties:
+
+ - outputs a single interrupt signal to its interrupt controller parent
+
+ - contains one or more enable/status word pairs, which often appear at
+ different offsets in different blocks
+
+ - no atomic set/clear operations
+
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
- const: brcm,bcm7120-l2-intc
+ items:
+ - enum:
+ - brcm,bcm7120-l2-intc
+ - brcm,bcm3380-l2-intc
reg:
description: >
Specifies the base physical address and size of the registers
+ minItems: 1
+ maxItems: 4
interrupt-controller: true
@@ -121,3 +136,14 @@ examples:
brcm,int-map-mask = <0xeb8>, <0x140>;
brcm,int-fwd-mask = <0x7>;
};
+
+ - |
+ irq1_intc: interrupt-controller@...00020 {
+ compatible = "brcm,bcm3380-l2-intc";
+ reg = <0x10000024 0x4>, <0x1000002c 0x4>,
+ <0x10000020 0x4>, <0x10000028 0x4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>;
+ };
--
2.25.1
Powered by blists - more mailing lists