linux-kernel - RE: [RFC PATCH v2 0/5] Add hardware prefetch driver for A64FX and Intel processors

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Message-ID: <OSBPR01MB203786A1B30C94950DFC50C2806D9@OSBPR01MB2037.jpnprd01.prod.outlook.com>
Date:   Mon, 6 Dec 2021 09:30:12 +0000
From:   "tarumizu.kohei@...itsu.com" <tarumizu.kohei@...itsu.com>
To:     'Borislav Petkov' <bp@...en8.de>
CC:     "'catalin.marinas@....com'" <catalin.marinas@....com>,
        "'will@...nel.org'" <will@...nel.org>,
        "'tglx@...utronix.de'" <tglx@...utronix.de>,
        "'mingo@...hat.com'" <mingo@...hat.com>,
        "'dave.hansen@...ux.intel.com'" <dave.hansen@...ux.intel.com>,
        "'x86@...nel.org'" <x86@...nel.org>,
        "'hpa@...or.com'" <hpa@...or.com>,
        "'linux-arm-kernel@...ts.infradead.org'" 
        <linux-arm-kernel@...ts.infradead.org>,
        "'linux-kernel@...r.kernel.org'" <linux-kernel@...r.kernel.org>
Subject: RE: [RFC PATCH v2 0/5] Add hardware prefetch driver for A64FX and
 Intel processors

>> Also, as dhansen points out, we have already
>> 
>>   /sys/devices/system/cpu/cpu*/cache
>> 
>> so all those knobs belong there on x86.
> 
> Intel MSR and A64FX have hardware prefetcher that affect L1d cache and
> L2 cache. Does it suit your intention to create a prefetcher directory
> under the cache directory as below?
> 
> /sys/devices/system/cpu/cpu*/cache/
>                 index0/prefetcher/enable
>                 index2/prefetcher/enable
> 
> The above example presumes that the L1d cache is at index0 (level: 1,
> type: Data) and the L2 cache is at index2 (level:2, type: Unified).

Any comment or suggestion would be much appreciated. In particular,
is our using cache/index directory above match your intent?