linux-kernel - [PATCH] soc/tegra: fuse: update nvmem cell list

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Date:   Mon, 6 Dec 2021 17:22:45 +0530
From:   Kartik <kkartik@...dia.com>
To:     <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <jonathanh@...dia.com>, <thierry.reding@...il.com>,
        <digetx@...il.com>
CC:     <kkartik@...dia.com>, <smangipudi@...dia.com>, <pshete@...dia.com>
Subject: [PATCH] soc/tegra: fuse: update nvmem cell list

From: kartik <kkartik@...dia.com>

Update tegra_fuse_cells with below entries:
 - gcplex-config-fuse:
     Configuration bits for GPU, used to enable/disable write protected
     region used for storing GPU firmware.
 - pdi0:
     Unique per chip public identifier.
 - pdi1:
     Unique per chip public identifier.

Signed-off-by: Prathamesh Shete <pshete@...dia.com>
Signed-off-by: kartik <kkartik@...dia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index f215181..c65252e 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2021, NVIDIA CORPORATION.  All rights reserved.
  */
 
 #include <linux/clk.h>
@@ -161,6 +161,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
 		.bit_offset = 0,
 		.nbits = 32,
 	}, {
+		.name = "gcplex-config-fuse",
+		.offset = 0x1c8,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
 		.name = "tsensor-realignment",
 		.offset = 0x1fc,
 		.bytes = 4,
@@ -178,6 +184,18 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
 		.bytes = 4,
 		.bit_offset = 0,
 		.nbits = 32,
+	}, {
+		.name = "pdi0",
+		.offset = 0x300,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
+	}, {
+		.name = "pdi1",
+		.offset = 0x304,
+		.bytes = 4,
+		.bit_offset = 0,
+		.nbits = 32,
 	},
 };
 
-- 
2.7.4