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Message-ID: <c2bd4fd6fe2ead4d7478c1e4ed53c781@kernel.org>
Date: Mon, 06 Dec 2021 12:53:26 +0000
From: Marc Zyngier <maz@...nel.org>
To: "xianwei.zhao" <xianwei.zhao@...ogic.com>
Cc: linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Neil Armstrong <narmstrong@...libre.com>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH] arm64: dts: add support for S4 based Amlogic AQ222
On 2021-12-06 10:02, xianwei.zhao wrote:
> Add basic support for the Amlogic S4 based Amlogic AQ222 board:
> which describe components as follows: CPU, GIC, IRQ, Timer, UART.
> It's capable of booting up into the serial console.
>
> Signed-off-by: xianwei.zhao <xianwei.zhao@...ogic.com>
> ---
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../dts/amlogic/meson-s4-s805x2-aq222.dts | 30 ++++++
> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 98 +++++++++++++++++++
> 3 files changed, 129 insertions(+)
> create mode 100644
> arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
> b/arch/arm64/boot/dts/amlogic/Makefile
> index 5148cd9e5146..faea74a45994 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -57,3 +57,4 @@ dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> new file mode 100644
> index 000000000000..6b6ecb40be4a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-s4.dtsi"
> +
> +/ {
> + model = "Amlogic";
> + compatible = "amlogic, aq222";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &uart_B;
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + linux,usable-memory = <0x0 0x0 0x0 0x40000000>;
> + };
> +
> +};
> +
> +&uart_B {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> new file mode 100644
> index 000000000000..b66f62701063
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> @@ -0,0 +1,98 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +/ {
> + cpus:cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0:cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35","arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + };
> +
> + CPU1:cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35","arm,armv8";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + };
> +
> + CPU2:cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35","arm,armv8";
> + reg = <0x0 0x2>;
> + enable-method = "psci";
> + };
> +
> + CPU3:cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a35","arm,armv8";
> + reg = <0x0 0x3>;
> + enable-method = "psci";
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 0xff08>,
> + <GIC_PPI 14 0xff08>,
> + <GIC_PPI 11 0xff08>,
> + <GIC_PPI 10 0xff08>;
You only have 4 CPUs, so the affinity is wrong. Please use
symbolic constants for all the PPIs.
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + xtal: xtal-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xtal";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic: interrupt-controller@...01000 {
> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
Neither, really. It cannot be an A9 GIC (you have virtualisation),
and because on an ARMv8 system, it is the CPU that implements
the CPU interface, this cannot be a A15 GIC either.
This is most likely yet another GIC400.
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0x0 0xfff01000 0 0x1000>,
> + <0x0 0xfff02000 0 0x0100>;
256 bytes? where are you getting this value from? You are also missing
the GICH and GICV regions, despite describing a maintenance interrupt...
> + interrupts = <GIC_PPI 9 0xf04>;
> + };
> +
> + apb4: apb4@...00000 {
> + compatible = "simple-bus";
> + reg = <0x0 0xfe000000 0x0 0x480000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
> +
> + uart_B: serial@...00 {
> + compatible = "amlogic,meson-gx-uart",
> + "amlogic,meson-ao-uart";
> + reg = <0x0 0x7a000 0x0 0x18>;
> + interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
> + status = "disabled";
> + clocks = <&xtal>, <&xtal>, <&xtal>;
> + clock-names = "xtal", "pclk", "baud";
> + xtal_tick_en = <1>;
> + fifo-size = <64>;
> + };
> + };
> + };
> +};
>
> base-commit: c5468e3c930d4d2937d3a842a85df0f74e95e152
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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