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Message-Id: <20211208173609.4064-18-digetx@gmail.com>
Date: Wed, 8 Dec 2021 20:36:02 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
David Heidelberg <david@...t.cz>,
Svyatoslav Ryhel <clamor95@...il.com>,
Anton Bambura <jenneron@...tonmail.com>,
Antoni Aloy Torrens <aaloytorrens@...il.com>,
Nikola Milosavljevic <mnidza@...look.com>,
Ion Agorria <ion@...rria.com>,
Michał Mirosław <mirq-linux@...e.qmqm.pl>,
Ihor Didenko <tailormoon@...bler.ru>,
Andreas Westman Dorcsak <hedmoo@...oo.com>,
Maxim Schwalm <maxim.schwalm@...il.com>,
Raffaele Tranquillini <raffaele.tranquillini@...il.com>,
Jasper Korten <jja2000@...il.com>,
Thomas Graichen <thomas.graichen@...il.com>,
Stefan Eichenberger <stefan.eichenberger@...adex.com>
Cc: devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v5 17/24] ARM: tegra: Enable CPU DFLL on Nyan
Enable CPU DFLL node on Nyan Chromebooks. DFLL was previously disabled due
to Linux kernel CPUFreq driver which didn't support suspend-resume. That
problem was fixed years ago, but DFLL was never re-enabled.
Tested-by: Thomas Graichen <thomas.graichen@...il.com> # T124 Nyan Big
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
arch/arm/boot/dts/tegra124-nyan.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a5dff226831b..ec01a23d4d47 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -532,7 +532,7 @@ mmc@...b0600 { /* eMMC on this bus */
/* CPU DFLL clock */
clock@...10000 {
- status = "disabled";
+ status = "okay";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,i2c-fs-rate = <400000>;
};
--
2.33.1
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