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Message-ID: <20211208174356.1997855-4-yazen.ghannam@amd.com>
Date:   Wed, 8 Dec 2021 17:43:55 +0000
From:   Yazen Ghannam <yazen.ghannam@....com>
To:     <linux-edac@...r.kernel.org>
CC:     <linux-kernel@...r.kernel.org>, <bp@...en8.de>,
        <mchehab@...nel.org>, <tony.luck@...el.com>, <james.morse@....com>,
        <rric@...nel.org>, <Smita.KoralahalliChannabasappa@....com>,
        <william.roche@...cle.com>, "Yazen Ghannam" <yazen.ghannam@....com>
Subject: [PATCH 3/4] EDAC/amd64: Check register values from all UMCs

Loop over all UMCs and create bitmasks to check the values of the
DIMM_CFG and UMC_CFG registers rather than just checking the values from
the first two UMCs.

Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
---
 drivers/edac/amd64_edac.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ff29267e46a6..1df763128483 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1621,9 +1621,16 @@ static void determine_memory_type(struct amd64_pvt *pvt)
 	u32 dram_ctrl, dcsm;
 
 	if (pvt->umc) {
-		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
+		u32 umc_cfg = 0, dimm_cfg = 0, i = 0;
+
+		for_each_umc(i) {
+			umc_cfg  |= pvt->umc[i].umc_cfg;
+			dimm_cfg |= pvt->umc[i].dimm_cfg;
+		}
+
+		if (dimm_cfg & BIT(5))
 			pvt->dram_type = MEM_LRDDR4;
-		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
+		else if (dimm_cfg & BIT(4))
 			pvt->dram_type = MEM_RDDR4;
 		else
 			pvt->dram_type = MEM_DDR4;
-- 
2.25.1

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