linux-kernel - Re: [PATCH v3 21/26] KVM: SVM: Drop AVIC's intermediate avic_set

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Message-ID: <f5b75c4d99c1f9e94ab9e639bc2fc8fddb9c7366.camel@redhat.com>
Date:   Wed, 08 Dec 2021 17:03:37 +0200
From:   Maxim Levitsky <mlevitsk@...hat.com>
To:     Paolo Bonzini <pbonzini@...hat.com>,
        Sean Christopherson <seanjc@...gle.com>,
        Joerg Roedel <joro@...tes.org>
Cc:     Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
        kvm@...r.kernel.org, iommu@...ts.linux-foundation.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 21/26] KVM: SVM: Drop AVIC's intermediate
 avic_set_running() helper

On Wed, 2021-12-08 at 15:43 +0100, Paolo Bonzini wrote:
> On 12/8/21 02:52, Sean Christopherson wrote:
> > +	/*
> > +	 * Unload the AVIC when the vCPU is about to block,_before_  the vCPU
> > +	 * actually blocks.  The vCPU needs to be marked IsRunning=0 before the
> > +	 * final pass over the vIRR via kvm_vcpu_check_block().  Any IRQs that
> > +	 * arrive before IsRunning=0 will not signal the doorbell, i.e. it's
> > +	 * KVM's responsibility to ensure there are no pending IRQs in the vIRR
> > +	 * after IsRunning is cleared, prior to scheduling out the vCPU.
> 
> I prefer to phrase this around paired memory barriers and the usual 
> store/smp_mb/load lockless idiom:
> 
> 	/*
> 	 * Unload the AVIC when the vCPU is about to block, _before_
> 	 * the vCPU actually blocks.
> 	 *
> 	 * Any IRQs that arrive before IsRunning=0 will not cause an
> 	 * incomplete IPI vmexit on the source, therefore vIRR will also
> 	 * be checked by kvm_vcpu_check_block() before blocking.  The
> 	 * memory barrier implicit in set_current_state orders writing

If I understand correctly this is a full memory barrier and not only a write barrier?

Also, just to document, I also found out that lack of subsequent vIRR checking
in the 'KVM: SVM: Unconditionally mark AVIC as running on vCPU load (with APICv)'
is what made AVIC totally unusable on my systems.
That patch would set is_running right in the middle of schedule() and then
no vIRR check would be done afterwards.

Small update on my adventures with AVIC: On two Milan machines I got my hands on,
on both AVIC is disabled in CPUID, but seems to work. None of my reproducers
manage to hit that errata and on top of that I have set of patches that make
AVIC co-exist with nesting and it appears to work while stress tested with
my KVM unit test which I updated to run a nested guest on one of the vCPUs.
I mostly testing the second machine though this week.

I'll post my patches as soon as I rebase them on top of this patch series,
after I review it.
I’ll post the unit test soon too.

Still my gut feeling is that the errata is still there - I am still waiting for
AMD to provide any info they could on this.

Best regards,
	Maxim Levitsky

> 	 * IsRunning=0 before reading the vIRR.  The processor needs a
> 	 * matching memory barrier on interrupt delivery between writing
> 	 * IRR and reading IsRunning; the lack of this barrier might be
> 	 * the cause of errata #1235).
> 	 */
> 
> Is there any nuance that I am missing?
> 
> Paolo
> 
> > +	 */
> > +	avic_vcpu_put(vcpu);
> > +