linux-kernel - Re: [PATCH 3/3] arm64: dts: imx8qxp: add cache info

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Message-ID: <CAL_JsqLD6=a==nx=aXjqRwQ3xTamrPVk8LwmqygC_q0UCrL9iw@mail.gmail.com>
Date:   Thu, 9 Dec 2021 16:15:09 -0600
From:   Rob Herring <robh+dt@...nel.org>
To:     "Peng Fan (OSS)" <peng.fan@....nxp.com>
Cc:     Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Lucas Stach <l.stach@...gutronix.de>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        devicetree@...r.kernel.org,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Peng Fan <peng.fan@....com>
Subject: Re: [PATCH 3/3] arm64: dts: imx8qxp: add cache info

On Fri, Nov 12, 2021 at 12:27 AM Peng Fan (OSS) <peng.fan@....nxp.com> wrote:
>
> From: Peng Fan <peng.fan@....com>
>
> i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
>  - Icache is 2-way set associative
>  - Dcache is 4-way set associative
>  - L2cache is 8-way set associative
>  - Line size are 64bytes
>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 617618edf77e..dbec7c106e0b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -58,6 +58,12 @@ A35_0: cpu@0 {
>                         compatible = "arm,cortex-a35";
>                         reg = <0x0 0x0>;
>                         enable-method = "psci";
> +                       i-cache-size = <0x8000>;
> +                       i-cache-line-size = <64>;
> +                       i-cache-sets = <256>;
> +                       d-cache-size = <0x8000>;
> +                       d-cache-line-size = <64>;
> +                       d-cache-sets = <128>;

Why do you need all this for the L1? Isn't it discoverable with cache
ID registers?

Rob