linux-kernel - Re: [PATCH v2 2/2] clk: qcom: Add clock driver for SM8450

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20211209082537.1AF6CC341C8@smtp.kernel.org>
Date:   Thu, 09 Dec 2021 00:25:35 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, Vinod Koul <vkoul@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, Vinod Koul <vkoul@...nel.org>,
        Andy Gross <agross@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Vamsi Krishna Lanka <quic_vamslank@...cinc.com>,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] clk: qcom: Add clock driver for SM8450

Quoting Vinod Koul (2021-12-07 03:40:03)
> diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
> new file mode 100644
> index 000000000000..82ac419718d7
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sm8450.c
> @@ -0,0 +1,3303 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2021, Linaro Limited
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-sm8450.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> +       P_BI_TCXO,
> +       P_GCC_GPLL0_OUT_EVEN,
> +       P_GCC_GPLL0_OUT_MAIN,
> +       P_GCC_GPLL4_OUT_MAIN,
> +       P_GCC_GPLL9_OUT_MAIN,
> +       P_PCIE_0_PIPE_CLK,
> +       P_PCIE_1_PHY_AUX_CLK,
> +       P_PCIE_1_PIPE_CLK,
> +       P_SLEEP_CLK,
> +       P_UFS_PHY_RX_SYMBOL_0_CLK,
> +       P_UFS_PHY_RX_SYMBOL_1_CLK,
> +       P_UFS_PHY_TX_SYMBOL_0_CLK,
> +       P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
> +};
> +
> +static struct clk_alpha_pll gcc_gpll0 = {
> +       .offset = 0x0,
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> +       .clkr = {
> +               .enable_reg = 0x62018,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_gpll0",
> +                       .parent_data = &(const struct clk_parent_data){
> +                               .fw_name = "bi_tcxo",

Maybe you want to drop these strings and use the dt index directly? That
may actually be faster because we don't do as many string comparisons
and the code may be smaller if we don't have to store bi_tcxo. I suppose
to make it more readable we could have #defines for each DT index like

 #define DT_BI_TCXO	0
 #define DT_SLEEP_CLK	1

Blaze a new trail!

> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
> +               },
> +       },
> +};