linux-kernel - Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration

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Message-ID: <YbHuV/LpcZqOTuLV@matsya>
Date:   Thu, 9 Dec 2021 17:23:59 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Swapnil Kashinath Jakhade <sjakhade@...ence.com>
Cc:     "kishon@...com" <kishon@...com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Milind Parab <mparab@...ence.com>,
        "a-govindraju@...com" <a-govindraju@...com>
Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
 multilink configuration

On 02-12-21, 14:12, Swapnil Kashinath Jakhade wrote:
> Hi Vinod,
> 
> > -----Original Message-----
> > From: Vinod Koul <vkoul@...nel.org>
> > Sent: Thursday, November 25, 2021 10:41 AM
> > To: Swapnil Kashinath Jakhade <sjakhade@...ence.com>
> > Cc: kishon@...com; robh+dt@...nel.org; p.zabel@...gutronix.de; linux-
> > phy@...ts.infradead.org; linux-kernel@...r.kernel.org;
> > devicetree@...r.kernel.org; Milind Parab <mparab@...ence.com>; a-
> > govindraju@...com
> > Subject: Re: [PATCH v3 13/15] phy: cadence: Sierra: Add PCIe + QSGMII PHY
> > multilink configuration
> > 
> > EXTERNAL MAIL
> > 
> > 
> > On 24-11-21, 07:33, Swapnil Kashinath Jakhade wrote:
> > 
> > > > so this is pcie->qsgmii ->ssc/external/internal ... ok
> > > >
> > > > > +				[NO_SSC] =
> > > > &pcie_100_no_ssc_plllc_cmn_vals,
> > > > > +				[EXTERNAL_SSC] =
> > > > &pcie_100_ext_ssc_plllc_cmn_vals,
> > > > > +				[INTERNAL_SSC] =
> > > > &pcie_100_int_ssc_plllc_cmn_vals,
> > > > > +			},
> > > > >  		},
> > > > >  		[TYPE_USB] = {
> > > > >  			[TYPE_NONE] = {
> > > > >  				[EXTERNAL_SSC] =
> > > > &usb_100_ext_ssc_cmn_vals,
> > > > >  			},
> > > > >  		},
> > > > > +		[TYPE_QSGMII] = {
> > > > > +			[TYPE_PCIE] = {
> > > >
> > > > now it is reverse! qsgmii -> pcie -> ... why?
> > > >
> > > > what is meant by pcie->qsgmii and qsgmii-> pcie?
> > > >
> > >
> > > Multi-protocol configuration is done in 2 phases, each for one protocol.
> > > e.g. for PCIe + QSGMII case,
> > > [TYPE_PCIE][TYPE_QSGMII] will configure common and lane registers for
> > > PCIe and [TYPE_QSGMII][TYPE_PCIE] will configure common and lane
> > registers for QSGMII.
> > 
> > Then it should be always common + protocol or protocol + common, not
> > both please! Pls make an order and stick to it everywhere... If that is not
> > possible, I would like to understand why
> 
> Could you please elaborate what do you mean by
> " common + protocol or protocol + common, not both please!"?
> The order is same everywhere which is common + lane configuration for protocol 1
> and then for protocol 2. For multiprotocol case, PHY configuration is based on which
> protocols are operating simultaneously. So e.g.
> [TYPE_QSGMII][TYPE_PCIE] -> QSGMII configuration when other protocol is PCIe
> Which might be different than
> [TYPE_QSGMII][TYPE_*] -> QSGMII configuration with other protocol.

As I said I would like to understand what is the difference b/w
[TYPE_QSGMII][TYPE_PCIE] & [TYPE_PCIE][TYPE_QSGMII] and why?

-- 
~Vinod