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Message-ID: <21922806-e64c-1c41-1373-55603604cf34@gmail.com>
Date: Fri, 10 Dec 2021 15:57:00 +0900
From: Chanwoo Choi <cwchoi00@...il.com>
To: Samuel Holland <samuel@...lland.org>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Maxime Ripard <mripard@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Rob Herring <robh+dt@...nel.org>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-pm@...r.kernel.org, linux-sunxi@...ts.linux.dev,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 6/6] PM / devfreq: Add a driver for the sun8i/sun50i
MBUS
On 21. 11. 18. 오후 12:18, Samuel Holland wrote:
> This driver works by adjusting the divider on the DRAM controller's
> module clock. Thus there is no fixed set of OPPs, only "full speed" down
> to "quarter speed" (or whatever the maximum divider is on that variant).
>
> It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which
> takes care of updating registers during the critical section while DRAM
> is inaccessible.
>
> This driver should support several sunxi SoCs, starting with the A33,
> which have a DesignWare DDR3 controller with merged PHY register space
> and the matching MBUS register layout (so not A63 or later). However,
> the driver has only been tested on the A64/H5, so those are the only
> compatibles enabled for now.
>
> Acked-by: Chanwoo Choi <cw00.choi@...sung.com>
> Signed-off-by: Samuel Holland <samuel@...lland.org>
> ---
> drivers/devfreq/Kconfig | 8 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/sun8i-a33-mbus.c | 511 +++++++++++++++++++++++++++++++
> 3 files changed, 520 insertions(+)
> create mode 100644 drivers/devfreq/sun8i-a33-mbus.c
>
(snip)
Applied it. Thanks.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
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