linux-kernel - Re: [PATCH v2 4/6] KVM: x86/pmu: Add pmc->intr to refactor kvm_perf_overflow{

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Date:   Fri, 10 Dec 2021 18:11:26 +0800
From:   Like Xu <like.xu.linux@...il.com>
To:     Paolo Bonzini <pbonzini@...hat.com>,
        Jim Mattson <jmattson@...gle.com>
Cc:     Andi Kleen <ak@...ux.intel.com>,
        Kim Phillips <kim.phillips@....com>,
        Sean Christopherson <seanjc@...gle.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org, Like Xu <likexu@...cent.com>
Subject: Re: [PATCH v2 4/6] KVM: x86/pmu: Add pmc->intr to refactor
 kvm_perf_overflow{_intr}()

On 10/12/2021 5:35 pm, Paolo Bonzini wrote:
> On 12/10/21 01:54, Jim Mattson wrote:
>> On Thu, Dec 9, 2021 at 12:28 AM Like Xu <like.xu.linux@...il.com> wrote:
>>>
>>> On 9/12/2021 12:25 pm, Jim Mattson wrote:
>>>>
>>>> Not your change, but if the event is counting anything based on
>>>> cycles, and the guest TSC is scaled to run at a different rate from
>>>> the host TSC, doesn't the initial value of the underlying hardware
>>>> counter have to be adjusted as well, so that the interrupt arrives
>>>> when the guest's counter overflows rather than when the host's counter
>>>> overflows?
>>>
>>> I've thought about this issue too and at least the Intel Specification
>>> did not let me down on this detail:
>>>
>>>          "The counter changes in the VMX non-root mode will follow
>>>          VMM's use of the TSC offset or TSC scaling VMX controls"
>>

Emm, before I left Intel to play AMD, my hardware architect gave
me a verbal yes about any reported TSC values for vmx non-root mode
(including the Timed LBR or PEBS records or PT packages) as long as
we enable the relevant VM execution control bits.

Not sure if it's true for legacy platforms.

>> Where do you see this? I see similar text regarding TSC packets in the
>> section on Intel Processor Trace, but nothing about PMU counters
>> advancing at a scaled TSC frequency.
> 
> Indeed it seems quite unlikely that PMU counters can count fractionally.
> 
> Even for tracing the SDM says "Like the value returned by RDTSC, TSC packets 
> will include these adjustments, but other timing packets (such as MTC, CYC, and 
> CBR) are not impacted".  Considering that "stand-alone TSC packets are typically 
> generated only when generation of other timing packets (MTCs and CYCs) has 
> ceased for a period of time", I'm not even sure it's a good thing that the 
> values in TSC packets are scaled and offset.

There are some discussion that cannot be made public.

We recommend (as software developers) that any PMU enabled guest
should keep the host/guest TSC as a joint progression for
performance tuning since guest doesn't have AMPERF capability.

> 
> Back to the PMU, for non-architectural counters it's not really possible to know 
> if they count in cycles or not.  So it may not be a good idea to special case 
> the architectural counters.

Yes captain.
Let's see if we have real world challenges or bugs to explore this detail further.

> 
> Paolo
>