lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20211210175223.31131-9-flora.fu@mediatek.com>
Date:   Sat, 11 Dec 2021 01:52:19 +0800
From:   Flora Fu <flora.fu@...iatek.com>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Pi-Cheng Chen <pi-cheng.chen@...iatek.com>,
        Yong Wu <yong.wu@...iatek.com>
CC:     <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        Flora Fu <flora.fu@...iatek.com>,
        "JB Tsai" <jb.tsai@...iatek.com>
Subject: [PATCH 08/12] arm64: dts: mt8195: Add APU-IOMMU nodes

Add APU-IOMMI nodes.

Signed-off-by: Yong Wu <yong.wu@...iatek.com>
Signed-off-by: Flora Fu <flora.fu@...iatek.com>

---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 7e31e64e6b39..2f14e3326a2c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/mt8195-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8195-memory-port.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
 #include <dt-bindings/reset/ti-syscon.h>
@@ -1367,6 +1368,22 @@
 			#mbox-cells = <1>;
 		};
 
+		iommu_apu0: iommu@...10000 {
+			compatible = "mediatek,mt8195-iommu-apu";
+			reg = <0 0x19010000 0 0x1000>;
+			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+			#iommu-cells = <1>;
+			power-domains = <&apuspm 0>;
+		};
+
+		iommu_apu1: iommu@...15000 {
+			compatible = "mediatek,mt8195-iommu-apu";
+			reg = <0 0x19015000 0 0x1000>;
+			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
+			#iommu-cells = <1>;
+			power-domains = <&apuspm 0>;
+		};
+
 		apu_conn: syscon@...20000 {
 			compatible = "mediatek,mt8195-apu-conn", "syscon";
 			reg = <0 0x19020000 0 0x1000>;
-- 
2.18.0

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ