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Message-ID: <CAHp75VeUn-a=Ob2i1Sxph3C4xa07yHMj7sg9R81R3STjQgSLiw@mail.gmail.com>
Date: Sun, 12 Dec 2021 21:16:13 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Felix Fietkau <nbd@....name>
Cc: linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>, john <john@...ozen.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>
Subject: Re: [PATCH v5 12/13] gpio: Add support for Airoha EN7523 GPIO controller
On Tue, Nov 30, 2021 at 1:08 AM Felix Fietkau <nbd@....name> wrote:
>
> From: John Crispin <john@...ozen.org>
>
> Airoha's GPIO controller on their ARM EN7523 SoCs consists of two banks of 32
> GPIOs. Each instance in DT is for an single bank.
a single
...
> +/**
> + * airoha_gpio_ctrl - Airoha GPIO driver data
> + *
Unnecessary blank line.
> + * @gc: Associated gpio_chip instance.
> + * @data: The data register.
> + * @dir0: The direction register for the lower 16 pins.
> + * @dir1: The direction register for the higher 16 pins.
> + * @output: The output enable register.
> + */
...
> +static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
> + int val, int out)
> +{
> + struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
> + u32 dir = ioread32(ctrl->dir[gpio / 16]);
> + u32 output = ioread32(ctrl->output);
> + u32 mask = BIT((gpio % 16) * 2);
> +
> + if (out) {
> + dir |= mask;
> + output |= BIT(gpio);
> + } else {
> + dir &= ~mask;
> + output &= ~BIT(gpio);
> + }
> +
> + iowrite32(dir, ctrl->dir[gpio / 16]);
> + iowrite32(output, ctrl->output);
> + if (out)
> + gc->set(gc, gpio, val);
Needs a fix or a comment to explain why it's fine that there is a
glitch possible.
> + return 0;
> +}
...
> + err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
> + NULL, NULL, NULL, 0);
> + if (err) {
> + dev_err(dev, "unable to init generic GPIO");
> + return err;
return dev_err_probe(...);
> + }
--
With Best Regards,
Andy Shevchenko
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