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Date:   Sun, 12 Dec 2021 16:26:18 +0900
From:   Hector Martin <marcan@...can.st>
To:     Marc Zyngier <maz@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Cc:     Mark Rutland <mark.rutland@....com>, Will Deacon <will@...nel.org>,
        Sven Peter <sven@...npeter.dev>,
        Alyssa Rosenzweig <alyssa@...enzweig.io>,
        Rob Herring <robh+dt@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Dougall <dougallj@...il.com>, kernel-team@...roid.com
Subject: Re: [PATCH v2 7/8] drivers/perf: arm_pmu: Handle 47 bit counters

On 01/12/2021 22.49, Marc Zyngier wrote:
> The current ARM PMU framework can only deal with 32 or 64bit counters.
> Teach it about a 47bit flavour.
> 
> Yes, this is odd.
> 
> Signed-off-by: Marc Zyngier <maz@...nel.org>
> ---
>   drivers/perf/arm_pmu.c       | 2 ++
>   include/linux/perf/arm_pmu.h | 2 ++
>   2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c
> index 295cc7952d0e..0a9ed1a061ac 100644
> --- a/drivers/perf/arm_pmu.c
> +++ b/drivers/perf/arm_pmu.c
> @@ -109,6 +109,8 @@ static inline u64 arm_pmu_event_max_period(struct perf_event *event)
>   {
>   	if (event->hw.flags & ARMPMU_EVT_64BIT)
>   		return GENMASK_ULL(63, 0);
> +	else if (event->hw.flags & ARMPMU_EVT_47BIT)
> +		return GENMASK_ULL(46, 0);
>   	else
>   		return GENMASK_ULL(31, 0);
>   }
> diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h
> index 2512e2f9cd4e..0407a38b470a 100644
> --- a/include/linux/perf/arm_pmu.h
> +++ b/include/linux/perf/arm_pmu.h
> @@ -26,6 +26,8 @@
>    */
>   /* Event uses a 64bit counter */
>   #define ARMPMU_EVT_64BIT		1
> +/* Event uses a 47bit counter */
> +#define ARMPMU_EVT_47BIT		2
>   
>   #define HW_OP_UNSUPPORTED		0xFFFF
>   #define C(_x)				PERF_COUNT_HW_CACHE_##_x
> 

Reviewed-by: Hector Martin <marcan@...can.st>

-- 
Hector Martin (marcan@...can.st)
Public Key: https://mrcn.st/pub

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