linux-kernel - [PATCH 5.15 032/171] platform/x86: amd-pmc: Fix s2idle failures on certain AMD laptops

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Date:   Mon, 13 Dec 2021 10:29:07 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Shyam Sundar S K <Shyam-sundar.S-k@....com>,
        Fabrizio Bertocci <fabriziobertocci@...il.com>,
        Hans de Goede <hdegoede@...hat.com>
Subject: [PATCH 5.15 032/171] platform/x86: amd-pmc: Fix s2idle failures on certain AMD laptops

From: Fabrizio Bertocci <fabriziobertocci@...il.com>

commit 49201b90af818654c5506a0decc18e111eadcb66 upstream.

On some AMD hardware laptops, the system fails communicating with the
PMC when entering s2idle and the machine is battery powered.

Hardware description: HP Pavilion Aero Laptop 13-be0097nr
CPU: AMD Ryzen 7 5800U with Radeon Graphics
GPU: 03:00.0 VGA compatible controller [0300]: Advanced Micro Devices,
Inc. [AMD/ATI] Device [1002:1638] (rev c1)

Detailed description of the problem (and investigation) here:
https://gitlab.freedesktop.org/drm/amd/-/issues/1799

Patch is a single line: reduce the polling delay in half, from 100uSec
to 50uSec when waiting for a change in state from the PMC after a
write command operation.

After changing the delay, I did not see a single failure on this
machine (I have this fix for now more than one week and s2idle worked
every single time on battery power).

Cc: stable@...r.kernel.org
Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@....com>
Signed-off-by: Fabrizio Bertocci <fabriziobertocci@...il.com>
Link: https://lore.kernel.org/r/CADtzkx7TdfbwtaVEXUdD6YXPey52E-nZVQNs+Z41DTx7gqMqtw@mail.gmail.com
Signed-off-by: Hans de Goede <hdegoede@...hat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 drivers/platform/x86/amd-pmc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/platform/x86/amd-pmc.c
+++ b/drivers/platform/x86/amd-pmc.c
@@ -70,7 +70,7 @@
 #define AMD_CPU_ID_CZN			AMD_CPU_ID_RN
 #define AMD_CPU_ID_YC			0x14B5

-#define PMC_MSG_DELAY_MIN_US		100
+#define PMC_MSG_DELAY_MIN_US		50
 #define RESPONSE_REGISTER_LOOP_MAX	20000

 #define SOC_SUBSYSTEM_IP_MAX	12