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Message-ID: <CAHp75VdL3hmr23CcJLDpvbHaKv5HrDZjmVQpCnRNmPM7nEx6WQ@mail.gmail.com>
Date: Tue, 14 Dec 2021 19:16:50 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Srinivasa Rao Mandadapu <quic_srivasam@...cinc.com>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Rob Herring <robh+dt@...nel.org>, plai@...eaurora.org,
Banajit Goswami <bgoswami@...eaurora.org>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
rohitkr@...eaurora.org, linux-arm-msm@...r.kernel.org,
ALSA Development Mailing List <alsa-devel@...a-project.org>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Stephen Boyd <swboyd@...omium.org>, judyhsiao@...omium.org,
Linus Walleij <linus.walleij@...aro.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Venkata Prasad Potturu <quic_potturu@...cinc.com>
Subject: Re: [PATCH v5 3/5] pinctrl: qcom: Extract chip specific LPASS LPI code
On Tue, Dec 14, 2021 at 7:15 PM Srinivasa Rao Mandadapu
<quic_srivasam@...cinc.com> wrote:
> On 12/8/2021 11:58 AM, Andy Shevchenko wrote:
...
> >> +#define NO_SLEW -1
> > Naming sucks for the header.
> >
> > LPI_NO_SLEW ?
>
> Actually it's already mainline code. Just these patches are
> rearrangement of old code.
>
> still do you suggest to change?
I would, but this means it should be in a separate change.
...
> >> +struct lpi_pingroup {
> >> + const char *name;
> >> + const unsigned int *pins;
> >> + unsigned int npins;
> >> + unsigned int pin;
> >> + /* Bit offset in slew register for SoundWire pins only */
> >> + int slew_offset;
> >> + unsigned int *funcs;
> >> + unsigned int nfuncs;
> >> +};
> > Are you going to convert this to use struct group_desc?
Any comments on this? It sounds like further improvements.
--
With Best Regards,
Andy Shevchenko
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