linux-kernel - Re: [PATCH v2 2/2] mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO reads as 32-bit reads.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 14 Dec 2021 12:42:21 +0200
From:   Adrian Hunter <adrian.hunter@...el.com>
To:     Hector Martin <marcan@...can.st>,
        Ben Chuang <benchuanggli@...il.com>,
        Ulf Hansson <ulf.hansson@...aro.org>
Cc:     Sven Peter <sven@...npeter.dev>, Marc Zyngier <maz@...nel.org>,
        linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 2/2] mmc: sdhci-pci-gli: GL975[50]: Issue 8/16-bit MMIO
 reads as 32-bit reads.

On 12/12/2021 09:02, Hector Martin wrote:
> For some reason, <32-bit reads do not work on Apple ARM64 platforms with
> these chips (even though they do on other PCIe devices). Issue them as
> 32-bit reads instead. This is done unconditionally, as it shouldn't hurt
> even if not necessary.
> 
> Signed-off-by: Hector Martin <marcan@...can.st>

Acked-by: Adrian Hunter <adrian.hunter@...el.com>

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index ad742743a494..c6828e84db31 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -906,7 +906,28 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
>  	return 0;
>  }
>  
> +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
> +
> +static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
> +{
> +	u32 val = readl(host->ioaddr + (reg & ~3));
> +	u16 word;
> +
> +	word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
> +	return word;
> +}
> +
> +static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
> +{
> +	u32 val = readl(host->ioaddr + (reg & ~3));
> +	u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
> +
> +	return byte;
> +}
> +
>  static const struct sdhci_ops sdhci_gl9755_ops = {
> +	.read_w			= sdhci_gli_readw,
> +	.read_b			= sdhci_gli_readb,
>  	.set_clock		= sdhci_gl9755_set_clock,
>  	.enable_dma		= sdhci_pci_enable_dma,
>  	.set_bus_width		= sdhci_set_bus_width,
> @@ -926,6 +947,8 @@ const struct sdhci_pci_fixes sdhci_gl9755 = {
>  };
>  
>  static const struct sdhci_ops sdhci_gl9750_ops = {
> +	.read_w			= sdhci_gli_readw,
> +	.read_b			= sdhci_gli_readb,
>  	.read_l                 = sdhci_gl9750_readl,
>  	.set_clock		= sdhci_gl9750_set_clock,
>  	.enable_dma		= sdhci_pci_enable_dma,
>