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Message-ID: <20211215141727.4901-5-yann.gautier@foss.st.com>
Date:   Wed, 15 Dec 2021 15:17:27 +0100
From:   Yann Gautier <yann.gautier@...s.st.com>
To:     Ulf Hansson <ulf.hansson@...aro.org>,
        Russell King <linux@...linux.org.uk>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Vladimir Zapolskiy <vz@...ia.com>,
        <u.kleine-koenig@...gutronix.de>, Marek Vasut <marex@...x.de>,
        Christophe Kerello <christophe.kerello@...s.st.com>,
        Ludovic Barre <ludovic.barre@...s.st.com>,
        <linux-mmc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>
CC:     Yann Gautier <yann.gautier@...s.st.com>
Subject: [PATCH 4/4] mmc: mmci: add hs200 support for stm32 sdmmc

Use feedback clock for HS200 mode, as for SDR104.
The HS200 mode can be enabled through DT by using mmc-hs200-1_8v.
It is possible to use it on STM32MP13, but not STM32MP15 platforms.

Signed-off-by: Ludovic Barre <ludovic.barre@...s.st.com>
Signed-off-by: Yann Gautier <yann.gautier@...s.st.com>
---
 drivers/mmc/host/mmci_stm32_sdmmc.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
index a75d3dd34d18..9c13f2c31365 100644
--- a/drivers/mmc/host/mmci_stm32_sdmmc.c
+++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
@@ -241,11 +241,12 @@ static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
 
 	/*
 	 * SDMMC_FBCK is selected when an external Delay Block is needed
-	 * with SDR104.
+	 * with SDR104 or HS200.
 	 */
 	if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
 		clk |= MCI_STM32_CLK_BUSSPEED;
-		if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
+		if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
+		    host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
 			clk &= ~MCI_STM32_CLK_SEL_MSK;
 			clk |= MCI_STM32_CLK_SELFBCK;
 		}
-- 
2.17.1

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