linux-kernel - Re: [PATCH V2 08/10] dt-bindings: media: nxp,imx8mq-vpu: Add support for G1 and G2 on imx8mm

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Date:   Thu, 16 Dec 2021 20:03:43 -0300
From:   Ezequiel Garcia <ezequiel@...guardiasur.com.ar>
To:     Adam Ford <aford173@...il.com>
Cc:     Rob Herring <robh@...nel.org>,
        linux-media <linux-media@...r.kernel.org>,
        Abel Vesa <abel.vesa@....com>,
        Adam Ford-BE <aford@...conembedded.com>,
        Benjamin Gaignard <benjamin.gaignard@...labora.com>,
        Hans Verkuil <hverkuil-cisco@...all.nl>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Lucas Stach <l.stach@...gutronix.de>,
        "open list:HANTRO VPU CODEC DRIVER" 
        <linux-rockchip@...ts.infradead.org>,
        devicetree <devicetree@...r.kernel.org>,
        arm-soc <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        "open list:STAGING SUBSYSTEM" <linux-staging@...ts.linux.dev>
Subject: Re: [PATCH V2 08/10] dt-bindings: media: nxp,imx8mq-vpu: Add support
 for G1 and G2 on imx8mm

Hi Adam,

On Thu, 16 Dec 2021 at 18:21, Adam Ford <aford173@...il.com> wrote:
>
> On Thu, Dec 16, 2021 at 3:07 PM Rob Herring <robh@...nel.org> wrote:
> >
> > On Thu, Dec 16, 2021 at 05:12:53AM -0600, Adam Ford wrote:
> > > The i.MX8M mini appears to have a similar G1 and G2 decoder but the
> > > post-procesing isn't present, so different compatible flags are requred.
> >
> > post-processing
> >
> > > Since all the other parameters are the same with imx8mq, just add
> > > the new compatible flags to nxp,imx8mq-vpu.yaml.
> > >
> > > Signed-off-by: Adam Ford <aford173@...il.com>
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> > > index c1e157251de7..b1f24c48c73b 100644
> > > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
> > > @@ -5,7 +5,7 @@
> > >  $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
> > >  $schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > >
> > > -title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
> > > +title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ/i.MX8MM SoCs
> >
> > Just 'i.MX8' so we don't have to change this everytime?
>
> Are you OK with i.MX8M?  8MQ, 8MM, and 8MP all appear to have G1 and
> G2 decoders.  The i.MX8 is different.
> >
> > >
> > >  maintainers:
> > >    - Philipp Zabel <p.zabel@...gutronix.de>
> > > @@ -20,6 +20,8 @@ properties:
> > >          deprecated: true
> > >        - const: nxp,imx8mq-vpu-g1
> > >        - const: nxp,imx8mq-vpu-g2
> > > +      - const: nxp,imx8mm-vpu-g1
> > > +      - const: nxp,imx8mm-vpu-g2
> >
> > Not compatible with the imx8mq variants?
>
> No, the structures associated with these compatible flags telling the
> driver what features are available have options for the post-processor
> in the 8MQ which are not present in the 8MM.
>

Just as G1 and G2 are different blocks, their "post-processor"
features are really different too.

The G2 core typically produces a tiled format, NV12_4L4,
and it an inline post-processor to convert that to linear NV12.

How does this work on the 8MM? What pixel format does it
produce natively?

It's hard to imagine the G2 block doesn't do linear NV12,
so I'm inclined to think it has that post-processing feature.

Thanks,
Ezequiel