linux-kernel - [PATCH 3/8] ARM: at91: ddr: fix typo to align with datasheet naming

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Date:   Thu, 16 Dec 2021 16:13:33 +0200
From:   Claudiu Beznea <claudiu.beznea@...rochip.com>
To:     <nicolas.ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
        <ludovic.desroches@...rochip.com>, <robh+dt@...nel.org>,
        <linux@...linux.org.uk>, <mturquette@...libre.com>,
        <sboyd@...nel.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: [PATCH 3/8] ARM: at91: ddr: fix typo to align with datasheet naming

Fix typo on UDDRC_PWRCTL.SELFREF_SW bitmask to align with datasheet
naming.

Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
 arch/arm/mach-at91/pm_suspend.S | 4 ++--
 include/soc/at91/sama7-ddr.h    | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index fdb4f63ecde4..abe4ced33eda 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -159,7 +159,7 @@ sr_ena_1:
 
 	/* Switch to self-refresh. */
 	ldr	tmp1, [r2, #UDDRC_PWRCTL]
-	orr	tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
+	orr	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
 	str	tmp1, [r2, #UDDRC_PWRCTL]
 
 sr_ena_2:
@@ -276,7 +276,7 @@ sr_dis_5:
 
 	/* Trigger self-refresh exit. */
 	ldr	tmp1, [r2, #UDDRC_PWRCTL]
-	bic	tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
+	bic	tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
 	str	tmp1, [r2, #UDDRC_PWRCTL]
 
 sr_dis_6:
diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
index 817b360efbb8..fee1b11bddca 100644
--- a/include/soc/at91/sama7-ddr.h
+++ b/include/soc/at91/sama7-ddr.h
@@ -53,7 +53,7 @@
 #define		UDDRC_STAT_OPMODE_MSK		(0x7 << 0)	/* Operating mode mask */
 
 #define UDDRC_PWRCTL				(0x30)		/* UDDRC Low Power Control Register */
-#define		UDDRC_PWRCTRL_SELFREF_SW	(1 << 5)	/* Software self-refresh */
+#define		UDDRC_PWRCTL_SELFREF_SW		(1 << 5)	/* Software self-refresh */
 
 #define UDDRC_DFIMISC				(0x1B0)		/* UDDRC DFI Miscellaneous Control Register */
 #define		UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0)	/* PHY initialization complete enable signal */
-- 
2.32.0