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Message-ID: <62714ae555a42dfccc992925691c44024d7d0e3a.camel@infradead.org>
Date:   Fri, 17 Dec 2021 19:26:31 +0000
From:   David Woodhouse <dwmw2@...radead.org>
To:     Tom Lendacky <thomas.lendacky@....com>,
        Thomas Gleixner <tglx@...utronix.de>
Cc:     Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "H . Peter Anvin" <hpa@...or.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        "Paul E . McKenney" <paulmck@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "rcu@...r.kernel.org" <rcu@...r.kernel.org>,
        "mimoja@...oja.de" <mimoja@...oja.de>,
        "hewenliang4@...wei.com" <hewenliang4@...wei.com>,
        "hushiyuan@...wei.com" <hushiyuan@...wei.com>,
        "luolongjun@...wei.com" <luolongjun@...wei.com>,
        "hejingxian@...wei.com" <hejingxian@...wei.com>
Subject: Re: [PATCH v3 0/9] Parallel CPU bringup for x86_64

On Fri, 2021-12-17 at 19:11 +0000, David Woodhouse wrote:
> I note that one is in native_write_msr() though. I wonder what it's
> writing?

CPU Reset (CPU 0)
RAX=0000000000000000 RBX=0000000000000202 RCX=0000000000000828 RDX=0000000000000000
RSI=0000000000000000 RDI=0000000000000828 RBP=0000000000000000 RSP=ffffc90000023ce0
R8 =0000000000000000 R9 =ffffc90000023b60 R10=0000000000000001 R11=0000000000000001
R12=000000000000069a R13=0000000000000005 R14=000000000000001c R15=0000000000000001
RIP=ffffffff810705c6 RFL=00000206 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0

It's writing zero (%rax/%rsi) to MSR 0x828 (%rcx/%rdi) which is the
X2APIC's APIC_ESR.

Can you reproduce this without the guest being in X2APIC mode? You'll
have to cut it back to only 254 vCPUs for that test.

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