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Message-ID: <CAMuHMdUiSnxmXFroHi1drcmkqkhshC+X=6mtw0_wFnS+P=O9Cw@mail.gmail.com>
Date: Fri, 17 Dec 2021 17:00:58 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Conor Dooley <Conor.Dooley@...rochip.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <bgolaszewski@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Jassi Brar <jassisinghbrar@...il.com>,
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Albert Ou <aou@...s.berkeley.edu>,
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Alexandre Belloni <alexandre.belloni@...tlin.com>,
Mark Brown <broonie@...nel.org>,
Greg KH <gregkh@...uxfoundation.org>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Lee Jones <lee.jones@...aro.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
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Atish Patra <atishp@...shpatra.org>
Subject: Re: [PATCH v2 14/17] riscv: dts: microchip: add fpga fabric section
to icicle kit
Hi Conor,
On Fri, Dec 17, 2021 at 4:32 PM <Conor.Dooley@...rochip.com> wrote:
> On 17/12/2021 13:43, Geert Uytterhoeven wrote:
> > On Fri, Dec 17, 2021 at 10:33 AM <conor.dooley@...rochip.com> wrote:
> >> From: Conor Dooley <conor.dooley@...rochip.com>
> >>
> >> Split the device tree for the Microchip MPFS into two sections by adding
> >> microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
> >> FPGA fabric.
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> >
> > Thanks for your patch!
> >
> >> --- /dev/null
> >> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> >> @@ -0,0 +1,13 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> >> +
> >> +/ {
> >> + corePWM0: pwm@...00000 {
> >> + compatible = "microchip,corepwm";
> >> + reg = <0x0 0x41000000 0x0 0xF0>;
> >> + microchip,sync-update = /bits/ 8 <0>;
> >> + #pwm-cells = <2>;
> >> + clocks = <&clkcfg CLK_FIC3>;
> >> + status = "disabled";
> >> + };
> >
> > I'm wondering if these should be grouped under a "fabric" subnode,
> > like we have an "soc" subnode for on-SoC devices? Rob?
> >
> > BTW, do you already have a naming plan for different revisions of
> > FPGA fabric cores?
> Not yet (assuming you mean specifically how we will handle it in the
> device tree) - although i was talking to someone about it yesterday.
> It's possible that we might handle that via a register, but if you have
> a suggestion or some precedence that you're aware of that would be useful.
>
> The actual naming convention of the IP cores themselves, yeah. I will
> dig it up for you on Monday.
I meant what if corepwm is enhanced, and how to detect that?
SiFive uses an integer version number, even for hard cores[1].
OpenCores uses an "-rtlsvnN" suffix (isn't svn dead? ;-)
No idea what e.g. LiteX and Microwatt are planning.
[1] Documentation/devicetree/bindings/sifive/sifive-blocks-ip-versioning.txt
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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