linux-kernel - Re: [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <881f056d-d1ed-c6de-c09d-6e84d8b14530@arm.com>
Date:   Fri, 17 Dec 2021 16:57:07 +0000
From:   Robin Murphy <robin.murphy@....com>
To:     Rob Herring <robh@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        James Morse <james.morse@....com>,
        Jeremy Linton <jeremy.linton@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Sudeep Holla <sudeep.holla@....com>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        Len Brown <lenb@...nel.org>, devicetree@...r.kernel.org,
        linux-acpi@...r.kernel.org
Subject: Re: [PATCH 2/6] cacheinfo: Set cache 'id' based on DT data

Hi Rob,

On 2021-12-16 23:31, Rob Herring wrote:
> Use the minimum CPU h/w id of the CPUs associated with the cache for the
> cache 'id'. This will provide a stable id value for a given system. As
> we need to check all possible CPUs, we can't use the shared_cpu_map
> which is just online CPUs. There's not a cache to CPUs mapping in DT, so
> we have to walk all CPU nodes and then walk cache levels.

I believe another expected use of the cache ID exposed in sysfs is to 
program steering tags for cache stashing (typically in VFIO-based 
userspace drivers like DPDK so we can't realistically mediate it any 
other way). There were plans afoot last year to ensure that ACPI PPTT 
could provide the necessary ID values for arm64 systems which will 
typically be fairly arbitrary (but unique) due to reflecting underlying 
interconnect routing IDs. Assuming that there will eventually be some 
interest in cache stashing on DT-based systems too, we probably want to 
allow for an explicit ID property on DT cache nodes in a similar manner.

That said, I think it does make sense to have some kind of 
auto-generated fallback scheme *as well*, since I'm sure there will be 
plenty systems which care about MPAM but don't support stashing, and 
therefore wouldn't have a meaningful set of IDs to populate their DT 
with. Conversely I think that might also matter for ACPI too - one point 
I remember from previous discussions is that PPTT may use a compact 
representation where a single entry represents all equivalent caches at 
that level, so I'm not sure we can necessarily rely on IDs out of that 
path being unique either.

Robin.

> Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
> Cc: "Rafael J. Wysocki" <rafael@...nel.org>
> Signed-off-by: Rob Herring <robh@...nel.org>
> ---
> v2:
>   - Loop with for_each_possible_cpu instead of for_each_of_cpu_node as
>     we will need the logical cpu numbers.
> ---
>   drivers/base/cacheinfo.c | 31 +++++++++++++++++++++++++++++++
>   1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
> index 66d10bdb863b..21accddf8f5f 100644
> --- a/drivers/base/cacheinfo.c
> +++ b/drivers/base/cacheinfo.c
> @@ -136,6 +136,36 @@ static bool cache_node_is_unified(struct cacheinfo *this_leaf,
>   	return of_property_read_bool(np, "cache-unified");
>   }
>   
> +static void cache_of_set_id(struct cacheinfo *this_leaf, struct device_node *np)
> +{
> +	int cpu;
> +	unsigned long min_id = ~0UL;
> +
> +	for_each_possible_cpu(cpu) {
> +		u64 id;
> +		struct device_node *cache_node, *cpu_node;
> +
> +		cache_node = cpu_node = of_get_cpu_node(cpu, NULL);
> +		id = of_get_cpu_hwid(cpu_node, 0);
> +		while ((cache_node = of_find_next_cache_node(cache_node))) {
> +			if (cache_node == np) {
> +				if (id < min_id) {
> +					min_id = id;
> +					of_node_put(cache_node);
> +					break;
> +				}
> +			}
> +			of_node_put(cache_node);
> +		}
> +		of_node_put(cpu_node);
> +	}
> +
> +	if (min_id != ~0UL) {
> +		this_leaf->id = min_id;
> +		this_leaf->attributes |= CACHE_ID;
> +	}
> +}
> +
>   static void cache_of_set_props(struct cacheinfo *this_leaf,
>   			       struct device_node *np)
>   {
> @@ -151,6 +181,7 @@ static void cache_of_set_props(struct cacheinfo *this_leaf,
>   	cache_get_line_size(this_leaf, np);
>   	cache_nr_sets(this_leaf, np);
>   	cache_associativity(this_leaf);
> +	cache_of_set_id(this_leaf, np);
>   }
>   
>   static int cache_setup_of_node(unsigned int cpu)