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Message-ID: <CAOMZO5BvLZYh3=q_-XNcw-v5wDcBpR3Qo26Gd3hTtJ_a-FQiuA@mail.gmail.com>
Date:   Mon, 20 Dec 2021 21:06:25 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     reinhold.mueller@...rion.com
Cc:     Rob Herring <robh+dt@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Shawn Guo <shawnguo@...nel.org>,
        NXP Linux Team <linux-imx@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 2/2] arm64: dts: imx8mm: Add support for emtrion
 emCON-MX8M Mini

Hi Reinhold,

On Mon, Dec 20, 2021 at 4:23 AM <reinhold.mueller@...rion.com> wrote:

> +       pinctrl_ecspi1: ecspi1-grp {
> +               fsl,pins = <
> +                       MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x82
> +                       MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x82
> +                       MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x82
> +               >;
> +       };
> +
> +       pinctrl_ecspi1_cs: ecspi1-cs {
> +               fsl,pins = <
> +                       MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x40000
> +                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x40000

This version looks good to me.

One nit: you seem to use a single SPI chipselect, but you add two entries here.

Is the MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 needed too?

Either way:

Reviewed-by: Fabio Estevam <festevam@...il.com>

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