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Message-Id: <20211221142417.19312-3-semen.protsenko@linaro.org>
Date: Tue, 21 Dec 2021 16:24:17 +0200
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Rob Herring <robh+dt@...nel.org>,
Sylwester Nawrocki <s.nawrocki@...sung.com>
Cc: Jaewon Kim <jaewon02.kim@...sung.com>,
Chanho Park <chanho61.park@...sung.com>,
David Virag <virag.david003@...il.com>,
Youngmin Nam <youngmin.nam@...sung.com>,
Tomasz Figa <tomasz.figa@...il.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Daniel Palmer <daniel@...f.com>,
Hao Fang <fanghao11@...wei.com>,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: [PATCH v5 2/2] arm64: dts: exynos: Add initial E850-96 board support
E850-96 is a 96boards development board manufactured by WinLink. It
incorporates Samsung Exynos850 SoC, and is compatible with 96boards
mezzanine boards [1], as it follows 96boards standards.
This patch adds minimal support for E850-96 board. Next features are
enabled in board dts file and verified with minimal BusyBox rootfs:
* User buttons
* LEDs
* Serial console
* Watchdog timers
* RTC
* eMMC
[1] https://www.96boards.org/products/mezzanine/
Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
---
Changes in v5:
- (none)
Changes in v4:
- Moved "rtcclk" clock to board dts file
- Specified "rtc_src" clock for rtc node in board dts file
- Specified "rtcclk" clock for cmu_hsi node in board dts file
- Improved comment for RAM memory node
Changes in v3:
- Ordered the pinctrl_alive phandle alphabetically (forgot to do so in
v2)
Changes in v2:
- Removed board_id and board_rev properties
- Removed BOARD_ID and BOARD_REV constants
- Put dtb in alphabetical order in Makefile
- Added "color" and "function" properties to LED nodes
- Sorted all phandle overrides by phandle name
- Removed 'broken-cd' property in eMMC node
- Added memory node
arch/arm64/boot/dts/exynos/Makefile | 1 +
.../boot/dts/exynos/exynos850-e850-96.dts | 195 ++++++++++++++++++
2 files changed, 196 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
index b41e86df0a84..be9df8e85c59 100644
--- a/arch/arm64/boot/dts/exynos/Makefile
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
exynos5433-tm2.dtb \
exynos5433-tm2e.dtb \
exynos7-espresso.dtb \
+ exynos850-e850-96.dtb \
exynosautov9-sadk.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
new file mode 100644
index 000000000000..7b5a61d22cc5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * WinLink E850-96 board device tree source
+ *
+ * Copyright (C) 2018 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2021 Linaro Ltd.
+ *
+ * Device tree source file for WinLink's E850-96 board which is based on
+ * Samsung Exynos850 SoC.
+ */
+
+/dts-v1/;
+
+#include "exynos850.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "WinLink E850-96 board";
+ compatible = "winlink,e850-96", "samsung,exynos850";
+
+ chosen {
+ stdout-path = &serial_0;
+ };
+
+ /*
+ * RAM: 4 GiB (eMCP):
+ * - 2 GiB at 0x80000000
+ * - 2 GiB at 0x880000000
+ *
+ * 0xbab00000..0xbfffffff: secure memory (85 MiB).
+ */
+ memory@...00000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x3ab00000>,
+ <0x0 0xc0000000 0x40000000>,
+ <0x8 0x80000000 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_voldown_pins &key_volup_pins>;
+
+ volume-down-key {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpa1 0 GPIO_ACTIVE_LOW>;
+ };
+
+ volume-up-key {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpa0 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* HEART_BEAT_LED */
+ user_led1: led-1 {
+ label = "yellow:user1";
+ gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_HEARTBEAT;
+ linux,default-trigger = "heartbeat";
+ };
+
+ /* eMMC_LED */
+ user_led2: led-2 {
+ label = "yellow:user2";
+ gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ linux,default-trigger = "mmc0";
+ };
+
+ /* SD_LED */
+ user_led3: led-3 {
+ label = "white:user3";
+ gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_SD;
+ linux,default-trigger = "mmc2";
+ };
+
+ /* WIFI_LED */
+ wlan_active_led: led-4 {
+ label = "yellow:wlan";
+ gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_YELLOW>;
+ function = LED_FUNCTION_WLAN;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ /* BLUETOOTH_LED */
+ bt_active_led: led-5 {
+ label = "blue:bt";
+ gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_BLUETOOTH;
+ linux,default-trigger = "hci0rx";
+ default-state = "off";
+ };
+ };
+
+ /*
+ * RTC clock (XrtcXTI); external, must be 32.768 kHz.
+ *
+ * TODO: Remove this once RTC clock is implemented properly as part of
+ * PMIC driver.
+ */
+ rtcclk: clock-rtcclk {
+ compatible = "fixed-clock";
+ clock-output-names = "rtcclk";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+};
+
+&cmu_hsi {
+ clocks = <&oscclk>, <&rtcclk>,
+ <&cmu_top CLK_DOUT_HSI_BUS>,
+ <&cmu_top CLK_DOUT_HSI_MMC_CARD>,
+ <&cmu_top CLK_DOUT_HSI_USB20DRD>;
+ clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
+ "dout_hsi_mmc_card", "dout_hsi_usb20drd";
+};
+
+&mmc_0 {
+ status = "okay";
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-highspeed;
+ non-removable;
+ mmc-hs400-enhanced-strobe;
+ card-detect-delay = <200>;
+ clock-frequency = <800000000>;
+ bus-width = <8>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <0 4>;
+ samsung,dw-mshc-ddr-timing = <2 4>;
+ samsung,dw-mshc-hs400-timing = <0 2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins
+ &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>;
+};
+
+&oscclk {
+ clock-frequency = <26000000>;
+};
+
+&pinctrl_alive {
+ key_voldown_pins: key-voldown-pins {
+ samsung,pins = "gpa1-0";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+
+ key_volup_pins: key-volup-pins {
+ samsung,pins = "gpa0-7";
+ samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
+ samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
+ samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
+ };
+};
+
+&rtc {
+ status = "okay";
+ clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>;
+ clock-names = "rtc", "rtc_src";
+};
+
+&serial_0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+};
+
+&usi_uart {
+ samsung,clkreq-on; /* needed for UART mode */
+ status = "okay";
+};
+
+&watchdog_cl0 {
+ status = "okay";
+};
+
+&watchdog_cl1 {
+ status = "okay";
+};
--
2.30.2
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