linux-kernel - Re: [PATCH v6 02/14] x86/msr: add AMD CPPC MSR definitions

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Message-ID: <YcH2hYJN9+NudhH4@zn.tnic>
Date:   Tue, 21 Dec 2021 16:45:09 +0100
From:   Borislav Petkov <bp@...e.de>
To:     Huang Rui <ray.huang@....com>
Cc:     "Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Shuah Khan <skhan@...uxfoundation.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...nel.org>,
        Giovanni Gherdovich <ggherdovich@...e.cz>,
        Steven Rostedt <rostedt@...dmis.org>, linux-pm@...r.kernel.org,
        Deepak Sharma <deepak.sharma@....com>,
        Alex Deucher <alexander.deucher@....com>,
        Mario Limonciello <mario.limonciello@....com>,
        Steven Noonan <steven@...vesoftware.com>,
        Nathan Fontenot <nathan.fontenot@....com>,
        Jinzhou Su <Jinzhou.Su@....com>,
        Xiaojian Du <Xiaojian.Du@....com>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH v6 02/14] x86/msr: add AMD CPPC MSR definitions

On Mon, Dec 20, 2021 at 12:35:16AM +0800, Huang Rui wrote:

Capitalize subject's first letter:
 [x86/msr: add AMD CPPC MSR definitions]
 [x86/msr: Add AMD CPPC MSR definitions]

> AMD CPPC (Collaborative Processor Performance Control) function uses MSR
> registers to manage the performance hints. So add the MSR register macro
> here.
> 
> Signed-off-by: Huang Rui <ray.huang@....com>
> ---
>  arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 01e2650b9585..e7945ef6a8df 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -486,6 +486,23 @@
>  
>  #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
>  
> +/* AMD Collaborative Processor Performance Control MSRs */
> +#define MSR_AMD_CPPC_CAP1		0xc00102b0
> +#define MSR_AMD_CPPC_ENABLE		0xc00102b1
> +#define MSR_AMD_CPPC_CAP2		0xc00102b2
> +#define MSR_AMD_CPPC_REQ		0xc00102b3
> +#define MSR_AMD_CPPC_STATUS		0xc00102b4
> +
> +#define CAP1_LOWEST_PERF(x)	(((x) >> 0) & 0xff)
> +#define CAP1_LOWNONLIN_PERF(x)	(((x) >> 8) & 0xff)
> +#define CAP1_NOMINAL_PERF(x)	(((x) >> 16) & 0xff)
> +#define CAP1_HIGHEST_PERF(x)	(((x) >> 24) & 0xff)
> +
> +#define REQ_MAX_PERF(x)		(((x) & 0xff) << 0)
> +#define REQ_MIN_PERF(x)		(((x) & 0xff) << 8)
> +#define REQ_DES_PERF(x)		(((x) & 0xff) << 16)
> +#define REQ_ENERGY_PERF_PREF(x)	(((x) & 0xff) << 24)

All those bitfield names are too generic - they should at least be
prefixed with "CPPC_"

If an Intel CPPC set of MSRs appears too, then the prefix should be
"AMD_CPPC_" and so on.

Thx.

-- 
Regards/Gruss,
    Boris.

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