linux-kernel - [PATCH 2/3] mmc:sunxi-mmc:fix clock division for timing mode

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Date:   Wed, 22 Dec 2021 11:15:21 +0800
From:   Michael Wu <michael@...winnertech.com>
To:     ulf.hansson@...aro.org, mripard@...nel.org, wens@...e.org,
        samuel@...lland.org, andre.przywara@....com
Cc:     jernej.skrabec@...il.com, linux-mmc@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
        linux-kernel@...r.kernel.org,
        Michael Wu <michael@...winnertech.com>
Subject: [PATCH 2/3] mmc:sunxi-mmc:fix clock division for timing mode

When use new timings,all speed mode requires a doubled module clock
if speed mode is ddr,requires a four times module clock
When use old timings,only 8 bit ddr requires a doubled module clock

Signed-off-by: Michael Wu <michael@...winnertech.com>
---
 drivers/mmc/host/sunxi-mmc.c | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index afeefead6501..7b47ec453fb6 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -774,20 +774,23 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 	if (!ios->clock)
 		return 0;
 
-	/*
-	 * Under the old timing mode, 8 bit DDR requires the module
-	 * clock to be double the card clock. Under the new timing
-	 * mode, all DDR modes require a doubled module clock.
-	 *
-	 * We currently only support the standard MMC DDR52 mode.
-	 * This block should be updated once support for other DDR
-	 * modes is added.
+	/**
+	 * When use new timings, all speed mode requires a doubled module clock.
+	 * if speed mode is ddr, requires a four times module clock.
+	 * When use old timings, only 8 bit ddr requires a doubled module clock.
 	 */
-	if (ios->timing == MMC_TIMING_MMC_DDR52 &&
-	    (host->use_new_timings ||
-	     ios->bus_width == MMC_BUS_WIDTH_8)) {
-		div = 2;
+	if (host->use_new_timings) {
 		clock <<= 1;
+		if (ios->timing == MMC_TIMING_MMC_DDR52) {
+			div = 2;
+			clock <<= 1;
+		}
+	} else {
+		if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+				(ios->bus_width == MMC_BUS_WIDTH_8)) {
+			div = 2;
+			clock <<= 1;
+		}
 	}
 
 	if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {
-- 
2.29.0