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Message-Id: <20211225115509.94891-3-hdegoede@redhat.com>
Date: Sat, 25 Dec 2021 12:55:07 +0100
From: Hans de Goede <hdegoede@...hat.com>
To: Mark Gross <markgross@...nel.org>,
Andy Shevchenko <andy@...radead.org>,
Lee Jones <lee.jones@...aro.org>
Cc: Hans de Goede <hdegoede@...hat.com>,
Stephan Gerhold <stephan@...hold.net>,
platform-driver-x86@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 2/4] mfd: intel_soc_pmic_crc: Add crystal_cove_charger cell to BYT cells
The Crystal Cove PMIC has a pin which can be used to connect the IRQ of
an external charger IC. On some boards this is used and we need to have
a cell for this, with a driver which creates its own irqchip with
a single IRQ for the charger driver to consume.
The charger driver cannot directly consume the IRQ from the MFD level
irqchip because the PMIC has 2 levels of interrupts and the second
level interrupt status register, which is handled by the cell drivers,
needs to have the IRQ acked to avoid an IRQ storm.
Signed-off-by: Hans de Goede <hdegoede@...hat.com>
---
drivers/mfd/intel_soc_pmic_crc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index 574cb8f9c70d..5bb0367bd974 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -44,6 +44,10 @@ static const struct resource adc_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
};
+static const struct resource charger_resources[] = {
+ DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_CHGR, "CHGR"),
+};
+
static const struct resource gpio_resources[] = {
DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
};
@@ -69,6 +73,11 @@ static struct mfd_cell crystal_cove_byt_dev[] = {
.num_resources = ARRAY_SIZE(adc_resources),
.resources = adc_resources,
},
+ {
+ .name = "crystal_cove_charger",
+ .num_resources = ARRAY_SIZE(charger_resources),
+ .resources = charger_resources,
+ },
{
.name = "crystal_cove_gpio",
.num_resources = ARRAY_SIZE(gpio_resources),
--
2.33.1
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