Message-ID: <1jzgomz26b.fsf@starbuckisacylon.baylibre.com>
Date:   Mon, 27 Dec 2021 12:58:34 +0100
From:   Jerome Brunet <jbrunet@...libre.com>
To:     Yu Tu <yu.tu@...ogic.com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     linux-serial@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jiri Slaby <jirislaby@...nel.org>,
        Neil Armstrong <narmstrong@...libre.com>,
        Kevin Hilman <khilman@...libre.com>
Subject: Re: [PATCH 3/3] tty: serial: meson: add UART driver compatible with
 S4 SoC on-chip


On Mon 27 Dec 2021 at 14:56, Yu Tu <yu.tu@...ogic.com> wrote:

> Hi Martin,
> 	Thank you very much for your reply.
>
> On 2021/12/25 1:25, Martin Blumenstingl wrote:
>> [ EXTERNAL EMAIL ]
>> Hello,
>> On Tue, Dec 21, 2021 at 8:17 AM Yu Tu <yu.tu@...ogic.com> wrote:
>>>
>>> The S4 SoC on-chip UART uses a 12M clock as the clock source for
>>> calculating the baud rate of the UART. But previously, chips used 24M or
>>> other clock sources. So add this change. The specific clock source is
>>> determined by chip design.
>> Does the new S4 SoC use an external 12MHz XTAL or does it use a 24MHz XTAL?
>> If there's still a 24MHz XTAL then I think this description is not
>> correct - at least based on how I understand the UART controller.
>> 
> The S4 SoC uses 12MHz(UART_EE_A_REG5[27]=0x1,the bit is set in
> romcode). This register description is the same as the G12A and G12B you
> know.
>
>> SoCs up to GXL and GXM had an internal divide-by-3 (clock divider) in
>> the UART controller IP and an external 24MHz XTAL.
>> This was not configurable, so the clock for all baud-rates had to be
>> derived from an 8MHz (24MHz divided by 3) clock.
>> With the A311D (G12B, which is still using an external 24MHz XTAL) SoC
>> the UART controller gained two new bits - with configurable dividers -
>> according to the public datasheets:
>> UART_EE_A_REG5[26]:
>> - 0x0: divide the input clock by 3 (meaning: this internally works
>> with an 8MHz clock)
>> - 0x1: use the input clock directly without further division (meaning:
>> this internally work with an 24MHz clock)
>> UART_EE_A_REG5[27]:
>> - 0x0: use the clock as configured in UART_EE_A_REG5[26]
>> - 0x1: divide the input clock by 2 (meaning: this internally works
>> with an 12MHz clock)
>> While writing this email I did some investigation and found that
>> UART_EE_A_REG5[26] is used in the vendor kernel even for GXL and GXM
>> SoCs.
>> So this probably has been introduced with the GXL generation (and thus
>> is missing on GXBB and earlier SoCs).
>> Also UART_EE_A_REG5[27] seems to have been introduced with the G12A
>> generation of SoCs (not surprising since G12A and G12B peripherals are
>> very similar).
>> Does the UART controller not work with divide-by-3 (as we have it
>> today) or are these configurable dividers to reduce jitter?
>> 
> The UART controller can work with divide-by-3.
> The chip history as you described above, the current reason for using 12MHz
> clock is really what you call reduce jitter. The UART mainly connects to
> Bluetooth and uses typical baud rates of 2Mhz, 3MHz and 4MHz, so 12MHz is
> used as the clock source.

Looks to me that the clock divider above should be modelled properly
with CCF. If you wish the initial Romcode setting to remain untouched,
then don't put CLK_SET_RATE_PARENT to stop rate propagation.

CCF will figure out what the internal rate is. You don't need to device
tree data if things are done properly

>> Best regards,
>> Martin
>> 

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