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Message-ID: <CAFBinCALAOJz16=u7r8tLM6ditriq=-NOACS2HRLrWs5B_FkVA@mail.gmail.com>
Date:   Thu, 30 Dec 2021 23:15:34 +0100
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     "Shunzhou.Jiang" <shunzhou.jiang@...ogic.com>
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Neil Armstrong <narmstrong@...libre.com>, khilman@...libre.com,
        jbrunet@...libre.com
Subject: Re: [PATCH V2 2/2] soc: s4: Add support for power domains controller

On Thu, Dec 30, 2021 at 10:44 AM Shunzhou.Jiang
<shunzhou.jiang@...ogic.com> wrote:
>
> From: Shunzhou Jiang <shunzhou.jiang@...ogic.com>
>
> Add support s4 Power controller. In s4, power control
> registers are in secure domain, and should be accessed by smc.
>
> Signed-off-by: Shunzhou Jiang <shunzhou.jiang@...ogic.com>
Also here I don't have any datasheet to compare this with, so this gets my:
Acked-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>

[...]
> +       SEC_PD(S4_VPU_HDMI,     GENPD_FLAG_ALWAYS_ON),
> +       SEC_PD(S4_USB_COMB,     GENPD_FLAG_ALWAYS_ON),
> +       SEC_PD(S4_GE2D,         0),
> +       SEC_PD(S4_ETH,          GENPD_FLAG_ALWAYS_ON),
For the A1 SoC's UART entry we have the following comment which
explains why we want to to be "always on":
  UART should keep working in ATF after suspend and before resume

If for some reason you need to re-send this series then it would be
great if you could add a comment above each entry with
GENPD_FLAG_ALWAYS_ON.
It will help others (like me) understand these SoCs better.


Best regards,
Martin

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