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Message-ID: <CAPLW+4k5cMUNvLkZNsJCqTfrFWOGiakerYHY3kc+xQAvQ2Ce6w@mail.gmail.com>
Date: Mon, 3 Jan 2022 16:45:02 +0200
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc: Tomasz Figa <tomasz.figa@...il.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Marek Szyprowski <m.szyprowski@...sung.com>,
Sylwester Nawrocki <snawrocki@...nel.org>,
Chanho Park <chanho61.park@...sung.com>
Subject: Re: [PATCH 19/24] arm64: dts: exynos: align pinctrl with dtschema in Exynos850
On Fri, 31 Dec 2021 at 18:23, Krzysztof Kozlowski
<krzysztof.kozlowski@...onical.com> wrote:
>
> Align the pin controller related nodes with dtschema. No functional
> change expected.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@...aro.org>
> .../boot/dts/exynos/exynos850-pinctrl.dtsi | 52 +++++++++----------
> 1 file changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> index f576b29c9b16..a71acf358d2d 100644
> --- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> @@ -13,7 +13,7 @@
> #include <dt-bindings/pinctrl/samsung.h>
>
> &pinctrl_alive {
> - gpa0: gpa0 {
> + gpa0: gpa0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -30,7 +30,7 @@ gpa0: gpa0 {
> <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpa1: gpa1 {
> + gpa1: gpa1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -47,7 +47,7 @@ gpa1: gpa1 {
> <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpa2: gpa2 {
> + gpa2: gpa2-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -64,7 +64,7 @@ gpa2: gpa2 {
> <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpa3: gpa3 {
> + gpa3: gpa3-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -81,7 +81,7 @@ gpa3: gpa3 {
> <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpa4: gpa4 {
> + gpa4: gpa4-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -94,7 +94,7 @@ gpa4: gpa4 {
> <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpq0: gpq0 {
> + gpq0: gpq0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -134,7 +134,7 @@ uart1_pins: uart1-pins {
> };
>
> &pinctrl_cmgp {
> - gpm0: gpm0 {
> + gpm0: gpm0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -144,7 +144,7 @@ gpm0: gpm0 {
> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpm1: gpm1 {
> + gpm1: gpm1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -154,7 +154,7 @@ gpm1: gpm1 {
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpm2: gpm2 {
> + gpm2: gpm2-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -164,7 +164,7 @@ gpm2: gpm2 {
> interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpm3: gpm3 {
> + gpm3: gpm3-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -174,7 +174,7 @@ gpm3: gpm3 {
> interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpm4: gpm4 {
> + gpm4: gpm4-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -184,7 +184,7 @@ gpm4: gpm4 {
> interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> - gpm5: gpm5 {
> + gpm5: gpm5-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -256,7 +256,7 @@ spi2_pins: spi2-pins {
> };
>
> &pinctrl_aud {
> - gpb0: gpb0 {
> + gpb0: gpb0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -264,7 +264,7 @@ gpb0: gpb0 {
> #interrupt-cells = <2>;
> };
>
> - gpb1: gpb1 {
> + gpb1: gpb1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -322,7 +322,7 @@ aud_fm_idle_pins: aud-fm-idle-pins {
> };
>
> &pinctrl_hsi {
> - gpf2: gpf2 {
> + gpf2: gpf2-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -367,7 +367,7 @@ sd2_pdn_pins: sd2-pdn-pins {
> };
>
> &pinctrl_core {
> - gpf0: gpf0 {
> + gpf0: gpf0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -375,7 +375,7 @@ gpf0: gpf0 {
> #interrupt-cells = <2>;
> };
>
> - gpf1: gpf1 {
> + gpf1: gpf1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -434,7 +434,7 @@ sd0_bus8_pins: sd0-bus8-pins {
> };
>
> &pinctrl_peri {
> - gpc0: gpc0 {
> + gpc0: gpc0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -442,7 +442,7 @@ gpc0: gpc0 {
> #interrupt-cells = <2>;
> };
>
> - gpc1: gpc1 {
> + gpc1: gpc1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -450,7 +450,7 @@ gpc1: gpc1 {
> #interrupt-cells = <2>;
> };
>
> - gpg0: gpg0 {
> + gpg0: gpg0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -458,7 +458,7 @@ gpg0: gpg0 {
> #interrupt-cells = <2>;
> };
>
> - gpg1: gpg1 {
> + gpg1: gpg1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -466,7 +466,7 @@ gpg1: gpg1 {
> #interrupt-cells = <2>;
> };
>
> - gpg2: gpg2 {
> + gpg2: gpg2-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -474,7 +474,7 @@ gpg2: gpg2 {
> #interrupt-cells = <2>;
> };
>
> - gpg3: gpg3 {
> + gpg3: gpg3-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -482,14 +482,14 @@ gpg3: gpg3 {
> #interrupt-cells = <2>;
> };
>
> - gpp0: gpp0 {
> + gpp0: gpp0-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> interrupt-controller;
> #interrupt-cells = <2>;
> };
> - gpp1: gpp1 {
> + gpp1: gpp1-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> @@ -497,7 +497,7 @@ gpp1: gpp1 {
> #interrupt-cells = <2>;
> };
>
> - gpp2: gpp2 {
> + gpp2: gpp2-gpio-bank {
> gpio-controller;
> #gpio-cells = <2>;
>
> --
> 2.32.0
>
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