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Date: Tue, 04 Jan 2022 04:14:18 +0000
From: Yassine Oudjana <y.oudjana@...tonmail.com>
To: Rob Herring <robh@...nel.org>
Cc: Yassine Oudjana <y.oudjana@...tonmail.com>,
Niklas Cassel <nks@...wful.org>,
Niklas Cassel <niklas.cassel@...aro.org>,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: power: avs: qcom,cpr: Convert to DT schema
On Tue, 21 Dec 2021 19:15:25 -0400, Rob Herring <robh@...nel.org> wrote:
> On Tue, Dec 21, 2021 at 01:40:05PM +0000, Yassine Oudjana wrote:
> > Convert qcom,cpr.txt to DT schema format.
> >
> > Signed-off-by: Yassine Oudjana <y.oudjana@...tonmail.com>
> > ---
> > .../bindings/power/avs/qcom,cpr.txt | 130 --------------
> > .../bindings/power/avs/qcom,cpr.yaml | 161 ++++++++++++++++++
> > MAINTAINERS | 2 +-
> > 3 files changed, 162 insertions(+), 131 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
> > create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
>
>
> > diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml b/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
> > new file mode 100644
> > index 000000000000..852eb36eea93
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
> > @@ -0,0 +1,161 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/power/avs/qcom,cpr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Core Power Reduction (CPR) bindings
> > +
> > +maintainers:
> > + - Niklas Cassel <nks@...wful.org>
> > +
> > +description: |
> > + CPR (Core Power Reduction) is a technology to reduce core power on a CPU
> > + or other device. Each OPP of a device corresponds to a "corner" that has
> > + a range of valid voltages for a particular frequency. While the device is
> > + running at a particular frequency, CPR monitors dynamic factors such as
> > + temperature, etc. and suggests adjustments to the voltage to save power
> > + and meet silicon characteristic requirements.
> > +
> > +properties:
> > + compatible:
> > + allOf:
>
> Don't need allOf with only 1 entry.
I get this from dt_binding_check without it:
Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml: properties:compatible: [{'items': [{'enum': ['qcom,qcs404-cpr']}, {'const': 'qcom,cpr'}]}] is not of type 'object', 'boolean'
>
> > + - items:
> > + - enum:
> > + - qcom,qcs404-cpr
> > + - const: qcom,cpr
> > +
> > + reg:
> > + description: Base address and size of the RBCPR register region.
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Reference clock.
> > +
> > + clock-names:
> > + items:
> > + - const: ref
> > +
> > + vdd-apc-supply:
> > + description: APC regulator supply.
> > +
> > + '#power-domain-cells':
> > + const: 0
> > +
> > + operating-points-v2:
> > + description: |
> > + A phandle to the OPP table containing the performance states
> > + supported by the CPR power domain.
> > +
> > + acc-syscon:
> > + description: A phandle to the syscon used for writing ACC settings.
> > +
> > + nvmem-cells:
> > + items:
> > + - description: Corner 1 quotient offset
> > + - description: Corner 2 quotient offset
> > + - description: Corner 3 quotient offset
> > + - description: Corner 1 initial voltage
> > + - description: Corner 2 initial voltage
> > + - description: Corner 3 initial voltage
> > + - description: Corner 1 quotient
> > + - description: Corner 2 quotient
> > + - description: Corner 3 quotient
> > + - description: Corner 1 ring oscillator
> > + - description: Corner 2 ring oscillator
> > + - description: Corner 3 ring oscillator
> > + - description: Fuse revision
> > +
> > + nvmem-cell-names:
> > + items:
> > + - const: cpr_quotient_offset1
> > + - const: cpr_quotient_offset2
> > + - const: cpr_quotient_offset3
> > + - const: cpr_init_voltage1
> > + - const: cpr_init_voltage2
> > + - const: cpr_init_voltage3
> > + - const: cpr_quotient1
> > + - const: cpr_quotient2
> > + - const: cpr_quotient3
> > + - const: cpr_ring_osc1
> > + - const: cpr_ring_osc2
> > + - const: cpr_ring_osc3
> > + - const: cpr_fuse_revision
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - vdd-apc-supply
> > + - '#power-domain-cells'
> > + - operating-points-v2
> > + - nvmem-cells
> > + - nvmem-cell-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + cpr_opp_table: cpr-opp-table {
> > + compatible = "operating-points-v2-qcom-level";
> > +
> > + cpr_opp1: opp1 {
> > + opp-level = <1>;
> > + qcom,opp-fuse-level = <1>;
> > + };
> > + cpr_opp2: opp2 {
> > + opp-level = <2>;
> > + qcom,opp-fuse-level = <2>;
> > + };
> > + cpr_opp3: opp3 {
> > + opp-level = <3>;
> > + qcom,opp-fuse-level = <3>;
> > + };
> > + };
> > +
> > + power-controller@...8000 {
> > + compatible = "qcom,qcs404-cpr", "qcom,cpr";
> > + reg = <0x0b018000 0x1000>;
> > + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> > + clocks = <&xo_board>;
> > + clock-names = "ref";
> > + vdd-apc-supply = <&pms405_s3>;
> > + #power-domain-cells = <0>;
> > + operating-points-v2 = <&cpr_opp_table>;
> > + acc-syscon = <&tcsr>;
> > +
> > + nvmem-cells = <&cpr_efuse_quot_offset1>,
> > + <&cpr_efuse_quot_offset2>,
> > + <&cpr_efuse_quot_offset3>,
> > + <&cpr_efuse_init_voltage1>,
> > + <&cpr_efuse_init_voltage2>,
> > + <&cpr_efuse_init_voltage3>,
> > + <&cpr_efuse_quot1>,
> > + <&cpr_efuse_quot2>,
> > + <&cpr_efuse_quot3>,
> > + <&cpr_efuse_ring1>,
> > + <&cpr_efuse_ring2>,
> > + <&cpr_efuse_ring3>,
> > + <&cpr_efuse_revision>;
> > + nvmem-cell-names = "cpr_quotient_offset1",
> > + "cpr_quotient_offset2",
> > + "cpr_quotient_offset3",
> > + "cpr_init_voltage1",
> > + "cpr_init_voltage2",
> > + "cpr_init_voltage3",
> > + "cpr_quotient1",
> > + "cpr_quotient2",
> > + "cpr_quotient3",
> > + "cpr_ring_osc1",
> > + "cpr_ring_osc2",
> > + "cpr_ring_osc3",
> > + "cpr_fuse_revision";
> > + };
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index a7d86182fa6b..9ebbccb0494e 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -15746,7 +15746,7 @@ M: Niklas Cassel <nks@...wful.org>
> > L: linux-pm@...r.kernel.org
> > L: linux-arm-msm@...r.kernel.org
> > S: Maintained
> > -F: Documentation/devicetree/bindings/power/avs/qcom,cpr.txt
> > +F: Documentation/devicetree/bindings/power/avs/qcom,cpr.yaml
> > F: drivers/soc/qcom/cpr.c
> >
> > QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
> > --
> > 2.34.1
> >
> >
> >
>
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