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Message-ID: <30161c1d-97f2-851e-7d57-6f604758f72f@microchip.com>
Date: Tue, 4 Jan 2022 08:02:10 +0000
From: <Tudor.Ambarus@...rochip.com>
To: <Kavyasree.Kotagiri@...rochip.com>, <arnd@...db.de>,
<olof@...om.net>, <robh+dt@...nel.org>,
<Nicolas.Ferre@...rochip.com>
CC: <soc@...nel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<Manohar.Puri@...rochip.com>
Subject: Re: [PATCH] ARM: dts: add DT for lan966x SoC and 2-port board pcb8291
On 1/3/22 2:48 PM, Kavyasree Kotagiri wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This patch adds basic DT for Microchip lan966x SoC and associated board
> pcb8291(2-port EVB). Adds peripherals required to allow booting: IRQs,
> clocks, timers, memory, flexcoms, GPIOs. Also adds other peripherals like
> crypto(AES,SHA), DMA and watchdog.
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
> ---
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/lan966x.dtsi | 235 ++++++++++++++++++++++++++
> arch/arm/boot/dts/lan966x_pcb8291.dts | 55 ++++++
> 3 files changed, 292 insertions(+)
> create mode 100644 arch/arm/boot/dts/lan966x.dtsi
> create mode 100644 arch/arm/boot/dts/lan966x_pcb8291.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 0de64f237cd8..dc1bd216ed58 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -723,6 +723,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> dtb-$(CONFIG_SOC_IMX7ULP) += \
> imx7ulp-com.dtb \
> imx7ulp-evk.dtb
> +dtb-$(CONFIG_SOC_LAN966) += \
> + lan966x_pcb8291.dtb
> dtb-$(CONFIG_SOC_LS1021A) += \
> ls1021a-moxa-uc-8410a.dtb \
> ls1021a-qds.dtb \
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> new file mode 100644
> index 000000000000..7e56394b036f
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -0,0 +1,235 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * lan966x.dtsi - Device Tree Include file for Microchip LAN966x family SoC
> + *
> + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
> + *
> + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/microchip,lan966x.h>
> +
> +/ {
> + model = "Microchip LAN966x family SoC";
> + compatible = "microchip,lan966x";
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + clock-frequency = <600000000>;
> + reg = <0x0>;
> + };
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>; /* 1GB */
> + };
> +
> + clocks {
> + sys_clk: sys_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <162500000>;
> + };
> +
> + cpu_clk: cpu_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + };
> +
> + ddr_clk: ddr_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <300000000>;
> + };
> +
> + nic_clk: nic_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> + };
> +
> + clks: clock-controller@...c00a8 {
> + compatible = "microchip,lan966x-gck";
> + #clock-cells = <1>;
> + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
> + clock-names = "cpu", "ddr", "sys";
> + reg = <0xe00c00a8 0x38>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <37500000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flx0: flexcom@...40000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0040000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0040000 0x800>;
> + status = "disabled";
> + };
> +
> + flx1: flexcom@...44000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0044000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0044000 0x800>;
> + status = "disabled";
> + };
> +
> + trng: trng@...48000 {
> + compatible = "atmel,at91sam9g45-trng";
> + reg = <0xe0048000 0x100>;
> + clocks = <&nic_clk>;
> + status = "disabled";
> + };
> +
> + aes: aes@...4c000 {
> + compatible = "atmel,at91sam9g46-aes";
> + reg = <0xe004c000 0x100>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
> + <&dma0 AT91_XDMAC_DT_PERID(12)>;
> + dma-names = "rx", "tx";
> + clocks = <&nic_clk>;
> + clock-names = "aes_clk";
status = "disabled";?
> + };
> +
> + flx2: flexcom@...60000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0060000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0060000 0x800>;
> + status = "disabled";
> + };
> +
> + flx3: flexcom@...64000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0064000 0x100>,
> + <0xe2004180 0x8>;
> + clocks = <&clks GCK_ID_FLEXCOM3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0064000 0x800>;
> + status = "disabled";
> + };
> +
> + dma0: dma-controller@...68000 {
> + compatible = "microchip,sama7g5-dma";
> + reg = <0xe0068000 0x1000>;
> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + clocks = <&nic_clk>;
> + clock-names = "dma_clk";
> + status = "okay";
> + };
> +
> + sha: sha@...6c000 {
> + compatible = "atmel,at91sam9g46-sha";
> + reg = <0xe006c000 0xec>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
> + dma-names = "tx";
> + clocks = <&nic_clk>;
> + clock-names = "sha_clk";
status?
> + };
> +
> + flx4: flexcom@...70000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0070000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0070000 0x800>;
> + status = "disabled";
> + };
> +
> + timer0: timer@...8c000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xe008c000 0x400>;
> + clocks = <&nic_clk>;
> + clock-names = "timer";
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@...90000 {
> + compatible = "snps,dw-wdt";
> + reg = <0xe0090000 0x1000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&nic_clk>;
status?
Cheers,
ta
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