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Date:   Wed, 5 Jan 2022 11:25:55 +0000
From:   Will Deacon <will@...nel.org>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Rob Herring <robh@...nel.org>, Mark Rutland <mark.rutland@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Vince Weaver <vincent.weaver@...ne.edu>,
        Jonathan Corbet <corbet@....net>,
        Catalin Marinas <catalin.marinas@....com>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Borislav Petkov <bp@...en8.de>,
        the arch/x86 maintainers <x86@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        linux-perf-users@...r.kernel.org,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>
Subject: Re: [PATCH v13 3/5] arm64: perf: Add userspace counter access
 disable switch

On Tue, Jan 04, 2022 at 01:56:59PM +0000, Will Deacon wrote:
> On Tue, Dec 28, 2021 at 12:07:02PM +0100, Geert Uytterhoeven wrote:
> > On Wed, Dec 8, 2021 at 9:19 PM Rob Herring <robh@...nel.org> wrote:
> > > Like x86, some users may want to disable userspace PMU counter
> > > altogether. Add a sysctl 'perf_user_access' file to control userspace
> > > counter access. The default is '0' which is disabled. Writing '1'
> > > enables access.
> > >
> > > Note that x86 supports globally enabling user access by writing '2' to
> > > /sys/bus/event_source/devices/cpu/rdpmc. As there's not existing
> > > userspace support to worry about, this shouldn't be necessary for Arm.
> > > It could be added later if the need arises.
> > 
> > Thanks for your patch, which is now commit e2012600810c9ded ("arm64:
> > perf: Add userspace counter access disable switch") in arm64/for-next/core.
> > 
> > This is causing two issues on Renesas Salvator-XS with R-Car H3.
> > One during kernel boot:
> > 
> >      hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7
> > counters available
> >     +sysctl duplicate entry: /kernel//perf_user_access
> >     +CPU: 0 PID: 1 Comm: swapper/0 Not tainted
> > 5.16.0-rc3-arm64-renesas-00003-ge2012600810c #1420
> >     +Hardware name: Renesas Salvator-X 2nd version board based on r8a77951 (DT)
> >     +Call trace:
> >     + dump_backtrace+0x0/0x190
> >     + show_stack+0x14/0x20
> >     + dump_stack_lvl+0x88/0xb0
> >     + dump_stack+0x14/0x2c
> >     + __register_sysctl_table+0x384/0x818
> >     + register_sysctl+0x20/0x28
> >     + armv8_pmu_init.constprop.0+0x118/0x150
> >     + armv8_a57_pmu_init+0x1c/0x28
> >     + arm_pmu_device_probe+0x1b4/0x558
> >     + armv8_pmu_device_probe+0x18/0x20
> >     + platform_probe+0x64/0xd0
> >     + really_probe+0xb4/0x2f8
> >     + __driver_probe_device+0x74/0xd8
> >     + driver_probe_device+0x3c/0xe0
> >     + __driver_attach+0x80/0x110
> >     + bus_for_each_dev+0x6c/0xc0
> >     + driver_attach+0x20/0x28
> >     + bus_add_driver+0x138/0x1e0
> >     + driver_register+0x60/0x110
> >     + __platform_driver_register+0x24/0x30
> >     + armv8_pmu_driver_init+0x18/0x20
> >     + do_one_initcall+0x15c/0x31c
> >     + kernel_init_freeable+0x2f0/0x354
> >     + kernel_init+0x20/0x120
> >     + ret_from_fork+0x10/0x20
> >      hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7
> > counters available
> > 
> > Presumably the same entry is added twice, once for the A53 PMU,
> > and a second time for the A57 PMU?
> 
> Looks like it, and perhaps that's also what is confusing systemd?
> Rob -- how come you didn't see this during your testing?
> 
> Anywho, please can you try the untested diff below?

I just remembered I have a big/little SoC on my desk after borrowing a
NanoPi (RK3399) from Marc Z, so I took this diff for a spin there and
both the kernel and systemd seem happy.

Will

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