linux-kernel - Re: [PATCH v3 4/9] dt-bindings: pinctrl: Add Nuvoton WPCM450

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Message-ID: <YdWt0zUh4ds1xlPz@latitude>
Date:   Wed, 5 Jan 2022 15:40:19 +0100
From:   Jonathan Neuschäfer <j.neuschaefer@....net>
To:     Rob Herring <robh@...nel.org>
Cc:     Jonathan Neuschäfer <j.neuschaefer@....net>,
        linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        Linus Walleij <linus.walleij@...aro.org>,
        openbmc@...ts.ozlabs.org, Tomer Maimon <tmaimon77@...il.com>,
        Joel Stanley <joel@....id.au>, linux-kernel@...r.kernel.org,
        Andy Shevchenko <andy.shevchenko@...il.com>,
        Avi Fishman <avifishman70@...il.com>,
        Tali Perry <tali.perry1@...il.com>,
        Patrick Venture <venture@...gle.com>,
        Nancy Yuen <yuenn@...gle.com>,
        Benjamin Fair <benjaminfair@...gle.com>
Subject: Re: [PATCH v3 4/9] dt-bindings: pinctrl: Add Nuvoton WPCM450

Hi,

On Tue, Jan 04, 2022 at 04:12:21PM -0600, Rob Herring wrote:
> On Fri, Dec 24, 2021 at 09:09:30PM +0100, Jonathan Neuschäfer wrote:
> > This binding is heavily based on the one for NPCM7xx, because the
> > hardware is similar. There are some notable differences, however:
> > 
> > - The addresses of GPIO banks are not physical addresses but simple
> >   indices (0 to 7), because the GPIO registers are not laid out in
> >   convenient blocks.
> > - Pinmux settings can explicitly specify that the GPIO mode is used.
> > 
> > Certain pins support blink patterns in hardware. This is currently not
> > modelled in the DT binding.
> > 
> > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@....net>
> > 
> > 
> > ---
[...]
> > +patternProperties:
> > +  # There are three kinds of subnodes:
> > +  # 1. a GPIO controller node for each GPIO bank
> > +  # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
> > +  # 3. a pinconf node configures properties of a single pin
> > +
> > +  "^gpio":
> 
> '^gpio@[0-7]$'

Makes sense, I'll change it.

> > +    type: object
> > +
> > +    description:
> > +      Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
> > +      GPIOs. Some GPIOs support interrupts.
> > +
> > +    properties:
> > +      reg:
> > +        description: GPIO bank number (0-7)
> 
> reg:
>   minimum: 0
>   maximum: 7
> 
> But there's not an actual register address range you could use instead?

Unfortunately no, not easily.

The GPIO bank specific registers are not arranged in a regular pattern,
so the address/offset of the first register in a bank does not suffice
to know the addresses of all other registers. Instead, different banks
support slightly different functionality (e.g. power source configurations
or automatic blinking), and the registers were crammed into the register
space as tightly as possible.

The full table of register offsets is in the driver, and for the
aforementioned reasons, a full table is necessary.


Thanks,
Jonathan Neuschäfer

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