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Date: Wed, 5 Jan 2022 13:13:55 -0800 From: Stephen Boyd <swboyd@...omium.org> To: Kuogee Hsieh <quic_khsieh@...cinc.com>, agross@...nel.org, airlied@...ux.ie, bjorn.andersson@...aro.org, daniel@...ll.ch, dmitry.baryshkov@...aro.org, robdclark@...il.com, sean@...rly.run, vkoul@...nel.org Cc: quic_abhinavk@...cinc.com, aravindh@...eaurora.org, quic_sbillaka@...cinc.com, freedreno@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org, linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org, Kuogee Hsieh <khsieh@...eaurora.org> Subject: Re: [PATCH v2] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3 Quoting Kuogee Hsieh (2021-12-29 10:15:45) > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h > index 6965afa..7dea101 100644 > --- a/drivers/gpu/drm/msm/dp/dp_catalog.h > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h > @@ -94,7 +94,7 @@ void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); > void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); > void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, > u32 stream_rate_khz, bool fixed_nvid); > -int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, u32 pattern); > +int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern); > void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); > bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog); > void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable); > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 39558a2..da6c083 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1078,12 +1078,13 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, > int tries, old_v_level, ret = 0; > u8 link_status[DP_LINK_STATUS_SIZE]; > int const maximum_retries = 4; > + char state_ctrl_bit = 1; > > dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0); > > *training_step = DP_TRAINING_1; > > - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, DP_TRAINING_PATTERN_1); > + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); Why not inline 'state_ctrl_bit' value of 1 here? > if (ret) > return ret; > dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | > @@ -1181,7 +1182,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > int *training_step) > { > int tries = 0, ret = 0; > - char pattern; > + char pattern, state_ctrl_bit; Why is 'state_ctrl_bit' a char when the function it's passed to takes a u32? Please be consistent with types. It would be good to make 'pattern' into a u8 as well instead of a char to be similarly consistent. > int const maximum_retries = 5; > u8 link_status[DP_LINK_STATUS_SIZE]; > > @@ -1189,12 +1190,20 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > > *training_step = DP_TRAINING_2; > > - if (drm_dp_tps3_supported(ctrl->panel->dpcd)) > + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { > + pattern = DP_TRAINING_PATTERN_4; > + state_ctrl_bit = 4; > + } > + else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { > pattern = DP_TRAINING_PATTERN_3; > - else > + state_ctrl_bit = 3; > + } > + else { > pattern = DP_TRAINING_PATTERN_2; > + state_ctrl_bit = 2; > + } > > - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); > + ret = dp_catalog_ctrl_set_pattern_state_bit(ctrl->catalog, state_ctrl_bit); > if (ret) > return ret; >
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