[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <3dfb1a06-4474-4614-08e5-b09f0977e03c@broadcom.com>
Date: Thu, 6 Jan 2022 13:37:12 +0100
From: Arend van Spriel <arend.vanspriel@...adcom.com>
To: Hector Martin <marcan@...can.st>,
Kalle Valo <kvalo@...eaurora.org>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Len Brown <lenb@...nel.org>,
Arend van Spriel <aspriel@...il.com>,
Franky Lin <franky.lin@...adcom.com>,
Hante Meuleman <hante.meuleman@...adcom.com>,
Chi-hsien Lin <chi-hsien.lin@...ineon.com>,
Wright Feng <wright.feng@...ineon.com>,
Dmitry Osipenko <digetx@...il.com>
Cc: Sven Peter <sven@...npeter.dev>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Mark Kettenis <kettenis@...nbsd.org>,
Rafał Miłecki <zajec5@...il.com>,
Pieter-Paul Giesberts <pieter-paul.giesberts@...adcom.com>,
Linus Walleij <linus.walleij@...aro.org>,
Hans de Goede <hdegoede@...hat.com>,
"John W. Linville" <linville@...driver.com>,
"brian m. carlson" <sandals@...stytoothpaste.net>,
Andy Shevchenko <andy.shevchenko@...il.com>,
linux-wireless@...r.kernel.org, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-acpi@...r.kernel.org, brcm80211-dev-list.pdl@...adcom.com,
SHA-cyfmac-dev-list@...ineon.com
Subject: Re: [PATCH v2 07/35] brcmfmac: pcie: Read Apple OTP information
On 1/4/2022 8:26 AM, Hector Martin wrote:
> On Apple platforms, the One Time Programmable ROM in the Broadcom chips
> contains information about the specific board design (module, vendor,
> version) that is required to select the correct NVRAM file. Parse this
> OTP ROM and extract the required strings.
>
> Note that the user OTP offset/size is per-chip. This patch does not add
> any chips yet.
Reviewed-by: Arend van Spriel <arend.vanspriel@...adcom.com>
> Signed-off-by: Hector Martin <marcan@...can.st>
> ---
> .../broadcom/brcm80211/brcmfmac/pcie.c | 219 ++++++++++++++++++
> include/linux/bcma/bcma_driver_chipcommon.h | 1 +
> 2 files changed, 220 insertions(+)
>
> diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
> index a52a6f8081eb..74c9a4f74813 100644
> --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
> +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
[...]
> +static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo)
> +{
> + const struct pci_dev *pdev = devinfo->pdev;
> + struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
> + u32 coreid, base, words, idx, sromctl;
> + u16 *otp;
> + struct brcmf_core *core;
> + int ret;
> +
> + switch (devinfo->ci->chip) {
> + default:
> + /* OTP not supported on this chip */
> + return 0;
> + }
Does not seem this code is put to work yet. Will dive into it later on.
> + core = brcmf_chip_get_core(devinfo->ci, coreid);
> + if (!core) {
> + brcmf_err(bus, "No OTP core\n");
> + return -ENODEV;
> + }
> +
> + if (coreid == BCMA_CORE_CHIPCOMMON) {
> + /* Chips with OTP accessed via ChipCommon need additional
> + * handling to access the OTP
> + */
> + brcmf_pcie_select_core(devinfo, coreid);
> + sromctl = READCC32(devinfo, sromcontrol);
> +
> + if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) {
> + /* Chip lacks OTP, try without it... */
> + brcmf_err(bus,
> + "OTP unavailable, using default firmware\n");
> + return 0;
> + }
> +
> + /* Map OTP to shadow area */
> + WRITECC32(devinfo, sromcontrol,
> + sromctl | BCMA_CC_SROM_CONTROL_OTPSEL);
> + }
> +
> + otp = kzalloc(sizeof(u16) * words, GFP_KERNEL);
> +
> + /* Map bus window to SROM/OTP shadow area in core */
> + base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base);
I guess this changes the bar window...
> + brcmf_dbg(PCIE, "OTP data:\n");
> + for (idx = 0; idx < words; idx++) {
> + otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx);
> + brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]);
> + }
> +
> + if (coreid == BCMA_CORE_CHIPCOMMON) {
> + brcmf_pcie_select_core(devinfo, coreid);
... which is why you need to reselect the core. Otherwise it makes no
sense to me.
> + WRITECC32(devinfo, sromcontrol, sromctl);
> + }
> +
> + ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words);
> + kfree(otp);
> +
> + return ret;
> +}
Download attachment "smime.p7s" of type "application/pkcs7-signature" (4219 bytes)
Powered by blists - more mailing lists