linux-kernel - Re: [PATCH v5 7/8] KVM: VMX: Update PID-pointer table entry when APIC ID is changed

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4eee5de5-ab76-7094-17aa-adc552032ba0@intel.com>
Date:   Thu, 6 Jan 2022 09:44:20 +0800
From:   Zeng Guang <guang.zeng@...el.com>
To:     Tom Lendacky <thomas.lendacky@....com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        "Christopherson,, Sean" <seanjc@...gle.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Joerg Roedel <joro@...tes.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        "Luck, Tony" <tony.luck@...el.com>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        Kim Phillips <kim.phillips@....com>,
        Jarkko Sakkinen <jarkko@...nel.org>,
        Jethro Beekman <jethro@...tanix.com>,
        "Huang, Kai" <kai.huang@...el.com>
Cc:     "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Hu, Robert" <robert.hu@...el.com>,
        "Gao, Chao" <chao.gao@...el.com>
Subject: Re: [PATCH v5 7/8] KVM: VMX: Update PID-pointer table entry when APIC
 ID is changed

On 1/6/2022 3:13 AM, Tom Lendacky wrote:
> On 12/31/21 8:28 AM, Zeng Guang wrote:
>> In xAPIC mode, guest is allowed to modify APIC ID at runtime.
>> If IPI virtualization is enabled, corresponding entry in
>> PID-pointer table need change accordingly.
>>
>> Signed-off-by: Zeng Guang <guang.zeng@...el.com>
>> ---
>>    arch/x86/include/asm/kvm_host.h |  1 +
>>    arch/x86/kvm/lapic.c            |  7 +++++--
>>    arch/x86/kvm/vmx/vmx.c          | 12 ++++++++++++
>>    3 files changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
>> index 2164b9f4c7b0..753bf2a7cebc 100644
>> --- a/arch/x86/include/asm/kvm_host.h
>> +++ b/arch/x86/include/asm/kvm_host.h
>> @@ -1493,6 +1493,7 @@ struct kvm_x86_ops {
>>    	int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err);
>>    
>>    	void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector);
>> +	void (*update_ipiv_pid_entry)(struct kvm_vcpu *vcpu, u8 old_id, u8 new_id);
>>    };
>>    
>>    struct kvm_x86_nested_ops {
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index 3ce7142ba00e..83c2c7594bcd 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -2007,9 +2007,12 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>>    
>>    	switch (reg) {
>>    	case APIC_ID:		/* Local APIC ID */
>> -		if (!apic_x2apic_mode(apic))
>> +		if (!apic_x2apic_mode(apic)) {
>> +			u8 old_id = kvm_lapic_get_reg(apic, APIC_ID) >> 24;
>> +
>>    			kvm_apic_set_xapic_id(apic, val >> 24);
>> -		else
>> +			kvm_x86_ops.update_ipiv_pid_entry(apic->vcpu, old_id, val >> 24);
> Won't this blow up on AMD since there is no corresponding SVM op?
>
> Thanks,
> Tom
Right, need check ops validness to avoid ruining AMD system. Same 
consideration on ops "update_ipiv_pid_table" in patch8.
I will revise in next version. Thanks.
>> +		} else
>>    			ret = 1;
>>    		break;
>>    
>>