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Date: Fri, 7 Jan 2022 15:53:20 -0800
From: Brian Norris <briannorris@...omium.org>
To: MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Rob Herring <robh+dt@...nel.org>
Cc: Heiko Stuebner <heiko@...ech.de>,
linux-arm-kernel@...ts.infradead.org,
Lin Huang <hl@...k-chips.com>, devicetree@...r.kernel.org,
linux-rockchip@...ts.infradead.org, linux-pm@...r.kernel.org,
Derek Basehore <dbasehore@...omium.org>,
linux-kernel@...r.kernel.org,
Enric Balletbo i Serra <enric.balletbo@...labora.com>,
Gaël PORTAY <gael.portay@...labora.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Brian Norris <briannorris@...omium.org>
Subject: [PATCH 10/10] arm64: dts: rockchip: Enable dmc and dfi nodes on gru
From: Lin Huang <hl@...k-chips.com>
Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY
Interface) nodes on gru boards so we can support DDR DVFS.
Signed-off-by: Lin Huang <hl@...k-chips.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
Signed-off-by: Gaël PORTAY <gael.portay@...labora.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
Signed-off-by: Brian Norris <briannorris@...omium.org>
---
This was part of a previous series, at:
https://lore.kernel.org/r/20210308233858.24741-3-daniel.lezcano@linaro.org
I've picked up a bunch of changes and fixes, so I've restarted the patch
series numbering.
Updates since the old series:
* reordered alphabetically by phandle name, per style
* drop a ton of deprecated/unused properties
* add required center-supply for scarlet
* add new *_idle_dis_freq properties
* drop the lowest (200 MHz) OPP; this was never stabilized for
production
* bump the voltage (0.9V -> 0.925V) for the highest OPP on Chromebook
models; later (tablet) models were more stable, with a fixed DDR
regulator
* bump odt_dis_freq to 666 MHz; early versions used 333 MHz, but
stabilization efforts landed on 666 MHz for production
.../dts/rockchip/rk3399-gru-chromebook.dtsi | 7 +++++
.../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 +++++++++++++++++++
.../boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index 9b2c679f5eca..46292fdceecb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -234,6 +234,13 @@ &cdn_dp {
extcon = <&usbc_extcon0>, <&usbc_extcon1>;
};
+&dmc {
+ center-supply = <&ppvar_centerlogic>;
+ rockchip,pd_idle_dis_freq = <800000000>;
+ rockchip,sr_idle_dis_freq = <800000000>;
+ rockchip,sr_mc_gate_idle_dis_freq = <800000000>;
+};
+
&edp {
status = "okay";
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
index a9817b3d7edc..913d845eb51a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
@@ -391,6 +391,18 @@ &cru {
<400000000>;
};
+/* The center supply is fixed to .9V on scarlet */
+&dmc {
+ center-supply = <&pp900_s0>;
+};
+
+/* We don't need .925 V for 928 MHz on scarlet */
+&dmc_opp_table {
+ opp03 {
+ opp-microvolt = <900000>;
+ };
+};
+
&gpio0 {
gpio-line-names = /* GPIO0 A 0-7 */
"CLK_32K_AP",
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 45a5ae5d2027..58b8d332f924 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -373,6 +373,34 @@ &cru {
<200000000>;
};
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ rockchip,pd_idle = <0x40>;
+ rockchip,sr_idle = <0x2>;
+ rockchip,sr_mc_gate_idle = <0x3>;
+ rockchip,srpd_lite_idle = <0x4>;
+ rockchip,standby_idle = <0x2000>;
+ rockchip,ddr3_odt_dis_freq = <666000000>;
+ rockchip,lpddr3_odt_dis_freq = <666000000>;
+ rockchip,lpddr4_odt_dis_freq = <666000000>;
+
+ rockchip,pd_idle_dis_freq = <1000000000>;
+ rockchip,sr_idle_dis_freq = <1000000000>;
+ rockchip,sr_mc_gate_idle_dis_freq = <1000000000>;
+ rockchip,srpd_lite_idle_dis_freq = <0>;
+ rockchip,standby_idle_dis_freq = <928000000>;
+};
+
+&dmc_opp_table {
+ opp03 {
+ opp-suspend;
+ };
+};
+
&emmc_phy {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
index 2180e0f75003..6e29e74f6fc6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
@@ -110,6 +110,27 @@ opp05 {
opp-microvolt = <1075000>;
};
};
+
+ dmc_opp_table: dmc_opp_table {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <928000000>;
+ opp-microvolt = <925000>;
+ };
+ };
};
&cpu_l0 {
@@ -136,6 +157,10 @@ &cpu_b1 {
operating-points-v2 = <&cluster1_opp>;
};
+&dmc {
+ operating-points-v2 = <&dmc_opp_table>;
+};
+
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
--
2.34.1.575.g55b058a8bb-goog
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