linux-kernel - Re: [PATCH 1/4] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220108005209.5140EC36AEB@smtp.kernel.org>
Date:   Fri, 07 Jan 2022 16:52:08 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Nikita Travkin <nikita@...n.ru>, linus.walleij@...aro.org,
        mturquette@...libre.com
Cc:     bjorn.andersson@...aro.org, agross@...nel.org, tdas@...eaurora.org,
        joonwoop@...eaurora.org, svarbanov@...sol.com,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
        ~postmarketos/upstreaming@...ts.sr.ht,
        Nikita Travkin <nikita@...n.ru>
Subject: Re: [PATCH 1/4] clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled.

Quoting Nikita Travkin (2021-12-09 08:37:17)
> In cases when MND is not enabled (e.g. when only Half Integer Divider is
> used), setting D registers makes no effect. Fail instead of making
> ineffective write.
> 
> Fixes: 7f891faf596e ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
> Signed-off-by: Nikita Travkin <nikita@...n.ru>
> ---
>  drivers/clk/qcom/clk-rcg2.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e1b1b426fae4..6964cf914b60 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -396,7 +396,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
>  static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
>  {
>         struct clk_rcg2 *rcg = to_clk_rcg2(hw);
> -       u32 notn_m, n, m, d, not2d, mask, duty_per;
> +       u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
>         int ret;
>  
>         /* Duty-cycle cannot be modified for non-MND RCGs */
> @@ -407,6 +407,11 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
>  
>         regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &notn_m);
>         regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
> +       regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
> +
> +       /* Duty-cycle cannot be modified if MND divider is in bypass mode. */
> +       if (!(cfg & CFG_MODE_MASK))
> +               return -EINVAL;

Should we still allow 50% duty cycle to succeed?