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Date: Wed, 12 Jan 2022 17:32:21 +0100
From: Yann Gautier <yann.gautier@...s.st.com>
To: Rob Herring <robh+dt@...nel.org>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
<devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>
CC: <linux-kernel@...r.kernel.org>, <linux-mmc@...r.kernel.org>,
Yann Gautier <yann.gautier@...s.st.com>
Subject: [PATCH 05/10] ARM: dts: stm32: update SDMMC clock slew-rate on STM32MP135F-DK board
Add sdmmc1_clk_pins_a in sdmmc1 pinctrl nodes, to properly manage
clock slew-rate.
Signed-off-by: Yann Gautier <yann.gautier@...s.st.com>
---
arch/arm/boot/dts/stm32mp135f-dk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts
index 7e96d9e36217..aae8d3512f4b 100644
--- a/arch/arm/boot/dts/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/stm32mp135f-dk.dts
@@ -39,8 +39,8 @@
&sdmmc1 {
pinctrl-names = "default", "opendrain";
- pinctrl-0 = <&sdmmc1_b4_pins_a>;
- pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
broken-cd;
disable-wp;
st,neg-edge;
--
2.17.1
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