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Message-ID: <202201140659.QkMQQEy9-lkp@intel.com>
Date: Fri, 14 Jan 2022 07:04:53 +0800
From: kernel test robot <lkp@...el.com>
To: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org,
Sean Christopherson <sean.j.christopherson@...el.com>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>,
Tony Luck <tony.luck@...el.com>
Subject: [intel-tdx:guest-upstream 25/33]
arch/x86/mm/pat/set_memory.c:2012:6: warning: variable 'ret' set but not
used
tree: https://github.com/intel/tdx.git guest-upstream
head: 33b1329c49e6d5f961b29c5cafd6571a5de523f0
commit: 5364ea9ede9af9f08041cacf140f8feef077d375 [25/33] x86/mm/cpa: Add support for TDX shared memory
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20220114/202201140659.QkMQQEy9-lkp@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/intel/tdx/commit/5364ea9ede9af9f08041cacf140f8feef077d375
git remote add intel-tdx https://github.com/intel/tdx.git
git fetch --no-tags intel-tdx guest-upstream
git checkout 5364ea9ede9af9f08041cacf140f8feef077d375
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash arch/x86/mm/pat/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
arch/x86/mm/pat/set_memory.c: In function '__set_memory_enc_pgtable':
>> arch/x86/mm/pat/set_memory.c:2012:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
2012 | int ret;
| ^~~
vim +/ret +2012 arch/x86/mm/pat/set_memory.c
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2004
810a521265023a1 arch/x86/mm/pat/set_memory.c Tianyu Lan 2021-10-25 2005 /*
810a521265023a1 arch/x86/mm/pat/set_memory.c Tianyu Lan 2021-10-25 2006 * __set_memory_enc_pgtable() is used for the hypervisors that get
810a521265023a1 arch/x86/mm/pat/set_memory.c Tianyu Lan 2021-10-25 2007 * informed about "encryption" status via page tables.
810a521265023a1 arch/x86/mm/pat/set_memory.c Tianyu Lan 2021-10-25 2008 */
810a521265023a1 arch/x86/mm/pat/set_memory.c Tianyu Lan 2021-10-25 2009 static int __set_memory_enc_pgtable(unsigned long addr, int numpages, bool enc)
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2010 {
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2011 struct cpa_data cpa;
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 @2012 int ret;
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2013
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2014 /* Should not be working on unaligned addresses */
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2015 if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr))
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2016 addr &= PAGE_MASK;
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2017
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2018 memset(&cpa, 0, sizeof(cpa));
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2019 cpa.vaddr = &addr;
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2020 cpa.numpages = numpages;
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2021
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2022 cpa.mask_set = pgprot_cc_mask(enc);
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2023 cpa.mask_clr = pgprot_cc_mask(!enc);
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2024
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2025 cpa.pgd = init_mm.pgd;
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2026
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2027 /* Must avoid aliasing mappings in the highmem code */
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2028 kmap_flush_unused();
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2029 vm_unmap_aliases();
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2030
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2031 /*
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2032 * Before changing the encryption attribute, flush caches.
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2033 *
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2034 * For TDX, guest is responsible for flushing caches on private->shared
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2035 * transition. VMM is responsible for flushing on shared->private.
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2036 */
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2037 if (cc_platform_has(CC_ATTR_GUEST_TDX)) {
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2038 if (!enc)
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2039 cpa_flush(&cpa, 1);
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2040 } else {
75d1cc0e05af579 arch/x86/mm/pat/set_memory.c Krish Sadhukhan 2020-09-17 2041 cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2042 }
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2043
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2044 ret = __change_page_attr_set_clr(&cpa, 1);
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2045
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2046 /*
fe0937b24ff5d7b arch/x86/mm/pageattr.c Peter Zijlstra 2018-12-03 2047 * After changing the encryption attribute, we need to flush TLBs again
fe0937b24ff5d7b arch/x86/mm/pageattr.c Peter Zijlstra 2018-12-03 2048 * in case any speculative TLB caching occurred (but no need to flush
fe0937b24ff5d7b arch/x86/mm/pageattr.c Peter Zijlstra 2018-12-03 2049 * caches again). We could just use cpa_flush_all(), but in case TLB
fe0937b24ff5d7b arch/x86/mm/pageattr.c Peter Zijlstra 2018-12-03 2050 * flushing gets optimized in the cpa_flush() path use the same logic
fe0937b24ff5d7b arch/x86/mm/pageattr.c Peter Zijlstra 2018-12-03 2051 * as above.
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2052 */
fe0937b24ff5d7b arch/x86/mm/pageattr.c Peter Zijlstra 2018-12-03 2053 cpa_flush(&cpa, 0);
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2054
064ce6c550a0630 arch/x86/mm/pat/set_memory.c Brijesh Singh 2021-08-24 2055 /*
064ce6c550a0630 arch/x86/mm/pat/set_memory.c Brijesh Singh 2021-08-24 2056 * Notify hypervisor that a given memory range is mapped encrypted
064ce6c550a0630 arch/x86/mm/pat/set_memory.c Brijesh Singh 2021-08-24 2057 * or decrypted.
064ce6c550a0630 arch/x86/mm/pat/set_memory.c Brijesh Singh 2021-08-24 2058 */
5364ea9ede9af9f arch/x86/mm/pat/set_memory.c Kirill A. Shutemov 2020-03-30 2059 return notify_range_enc_status_changed(addr, numpages, enc);
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2060 }
77bd2342d4304bd arch/x86/mm/pageattr.c Tom Lendacky 2017-07-17 2061
:::::: The code at line 2012 was first introduced by commit
:::::: 77bd2342d4304bda7896c953d424d15deb314ca3 x86/mm: Add support for changing the memory encryption attribute
:::::: TO: Tom Lendacky <thomas.lendacky@....com>
:::::: CC: Ingo Molnar <mingo@...nel.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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