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Message-ID: <f8b83cf0-7ebf-1ecd-b544-f0d0079d9dde@microchip.com>
Date: Thu, 13 Jan 2022 09:33:48 +0100
From: Nicolas Ferre <nicolas.ferre@...rochip.com>
To: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>,
<arnd@...db.de>, <olof@...om.net>, <soc@...nel.org>,
<robh+dt@...nel.org>
CC: <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<UNGLinuxDriver@...rochip.com>
Subject: Re: [PATCH v3] ARM: dts: add DT for lan966x SoC and 2-port board
pcb8291
On 13/01/2022 at 09:00, Kavyasree Kotagiri wrote:
> This patch adds basic DT for Microchip lan966x SoC and associated board
> pcb8291(2-port EVB). Adds peripherals required to allow booting: IRQs,
> clocks, timers, memory, flexcoms, GPIOs. Also adds other peripherals like
> crypto(AES,SHA), DMA and watchdog.
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
Looks good to me:
Reviewed-by: Nicolas Ferre <nicolas.ferre@...rochip.com>
Best regards,
Nicolas
> ---
> v2 -> v3:
> - Enabling trng in dtsi itself.
> - Removed "status=okay" dma0.
> - Add gpio pin settings for can0(missed adding this in previous version)
>
> v1 -> v2:
> - Moved flx3 usart0 node to dtsi file.
> - Removed status="okay" for dma0 to maintain consistency across nodes
> (which means enabling dma0 by default)
>
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/lan966x.dtsi | 242 ++++++++++++++++++++++++++
> arch/arm/boot/dts/lan966x_pcb8291.dts | 53 ++++++
> 3 files changed, 297 insertions(+)
> create mode 100644 arch/arm/boot/dts/lan966x.dtsi
> create mode 100644 arch/arm/boot/dts/lan966x_pcb8291.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 235ad559acb2..2040a990f08c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
> dtb-$(CONFIG_SOC_IMX7ULP) += \
> imx7ulp-com.dtb \
> imx7ulp-evk.dtb
> +dtb-$(CONFIG_SOC_LAN966) += \
> + lan966x_pcb8291.dtb
> dtb-$(CONFIG_SOC_LS1021A) += \
> ls1021a-moxa-uc-8410a.dtb \
> ls1021a-qds.dtb \
> diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
> new file mode 100644
> index 000000000000..d7bc36a998bc
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x.dtsi
> @@ -0,0 +1,242 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * lan966x.dtsi - Device Tree Include file for Microchip LAN966x family SoC
> + *
> + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
> + *
> + * Author: Kavyasree Kotagiri <kavyasree.kotagiri@...rochip.com>
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/clock/microchip,lan966x.h>
> +
> +/ {
> + model = "Microchip LAN966x family SoC";
> + compatible = "microchip,lan966x";
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + clock-frequency = <600000000>;
> + reg = <0x0>;
> + };
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>; /* 1GB */
> + };
> +
> + clocks {
> + sys_clk: sys_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <162500000>;
> + };
> +
> + cpu_clk: cpu_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + };
> +
> + ddr_clk: ddr_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <300000000>;
> + };
> +
> + nic_clk: nic_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> + };
> +
> + clks: clock-controller@...c00a8 {
> + compatible = "microchip,lan966x-gck";
> + #clock-cells = <1>;
> + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
> + clock-names = "cpu", "ddr", "sys";
> + reg = <0xe00c00a8 0x38>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <37500000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flx0: flexcom@...40000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0040000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0040000 0x800>;
> + status = "disabled";
> + };
> +
> + flx1: flexcom@...44000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0044000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0044000 0x800>;
> + status = "disabled";
> + };
> +
> + trng: trng@...48000 {
> + compatible = "atmel,at91sam9g45-trng";
> + reg = <0xe0048000 0x100>;
> + clocks = <&nic_clk>;
> + };
> +
> + aes: aes@...4c000 {
> + compatible = "atmel,at91sam9g46-aes";
> + reg = <0xe004c000 0x100>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
> + <&dma0 AT91_XDMAC_DT_PERID(12)>;
> + dma-names = "rx", "tx";
> + clocks = <&nic_clk>;
> + clock-names = "aes_clk";
> + };
> +
> + flx2: flexcom@...60000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0060000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM2>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0060000 0x800>;
> + status = "disabled";
> + };
> +
> + flx3: flexcom@...64000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0064000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM3>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0064000 0x800>;
> + status = "disabled";
> +
> + usart0: serial@200 {
> + compatible = "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&nic_clk>;
> + clock-names = "usart";
> + atmel,fifo-size = <32>;
> + status = "disabled";
> + };
> + };
> +
> + dma0: dma-controller@...68000 {
> + compatible = "microchip,sama7g5-dma";
> + reg = <0xe0068000 0x1000>;
> + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + clocks = <&nic_clk>;
> + clock-names = "dma_clk";
> + };
> +
> + sha: sha@...6c000 {
> + compatible = "atmel,at91sam9g46-sha";
> + reg = <0xe006c000 0xec>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
> + dma-names = "tx";
> + clocks = <&nic_clk>;
> + clock-names = "sha_clk";
> + };
> +
> + flx4: flexcom@...70000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0070000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0070000 0x800>;
> + status = "disabled";
> + };
> +
> + timer0: timer@...8c000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xe008c000 0x400>;
> + clocks = <&nic_clk>;
> + clock-names = "timer";
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@...90000 {
> + compatible = "snps,dw-wdt";
> + reg = <0xe0090000 0x1000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&nic_clk>;
> + };
> +
> + can0: can@...1c000 {
> + compatible = "bosch,m_can";
> + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
> + reg-names = "m_can", "message_ram";
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "int0", "int1";
> + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
> + clock-names = "hclk", "cclk";
> + assigned-clocks = <&clks GCK_ID_MCAN0>;
> + assigned-clock-rates = <40000000>;
> + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
> + status = "disabled";
> + };
> +
> + gpio: pinctrl@...04064 {
> + compatible = "microchip,lan966x-pinctrl";
> + reg = <0xe2004064 0xb4>,
> + <0xe2010024 0x138>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&gpio 0 0 78>;
> + interrupt-controller;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <2>;
> + };
> +
> + gic: interrupt-controller@...11000 {
> + compatible = "arm,gic-400", "arm,cortex-a7-gic";
> + #interrupt-cells = <3>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + reg = <0xe8c11000 0x1000>,
> + <0xe8c12000 0x2000>,
> + <0xe8c14000 0x2000>,
> + <0xe8c16000 0x2000>;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/lan966x_pcb8291.dts b/arch/arm/boot/dts/lan966x_pcb8291.dts
> new file mode 100644
> index 000000000000..cf54f42c763d
> --- /dev/null
> +++ b/arch/arm/boot/dts/lan966x_pcb8291.dts
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * lan966x_pcb8291.dts - Device Tree file for PCB8291
> + */
> +/dts-v1/;
> +#include "lan966x.dtsi"
> +
> +/ {
> + model = "Microchip EVB - LAN9662";
> + compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
> +};
> +
> +&gpio {
> + fc_shrd7_pins: fc_shrd7-pins {
> + pins = "GPIO_49";
> + function = "fc_shrd7";
> + };
> +
> + fc_shrd8_pins: fc_shrd8-pins {
> + pins = "GPIO_54";
> + function = "fc_shrd8";
> + };
> +
> + fc3_b_pins: fcb3-spi-pins {
> + /* SCK, RXD, TXD */
> + pins = "GPIO_51", "GPIO_52", "GPIO_53";
> + function = "fc3_b";
> + };
> +
> + can0_b_pins: can0_b_pins {
> + /* RX, TX */
> + pins = "GPIO_35", "GPIO_36";
> + function = "can0_b";
> + };
> +};
> +
> +&can0 {
> + pinctrl-0 = <&can0_b_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&flx3 {
> + atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
> + status = "okay";
> +
> + usart0: serial@200 {
> + pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> + };
> +};
> +
>
--
Nicolas Ferre
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